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ACM Transactions on Design Automation of Electronic Systems, Volume 25
Volume 25, Number 1, January 2020
- Rouhollah Mahfouzi, Amir Aminifar
, Soheil Samii, Petru Eles, Zebo Peng:
Security-aware Routing and Scheduling for Control Applications on Ethernet TSN Networks. 1:1-1:26 - Guoyong Shi:
Automatic Stage-form Circuit Reduction for Multistage Opamp Design Equation Generation. 2:1-2:26 - Chih-Hao Wang, Tong-Yu Hsieh:
An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications. 3:1-3:27 - Tamzidul Hoque, Kai Yang, Robert Karam, Shahin Tajik, Domenic Forte
Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks. 4:1-4:32 - Sukanta Bhattacharjee, Jack Tang, Sudip Poddar
Bio-chemical Assay Locking to Thwart Bio-IP Theft. 5:1-5:20 - Amin Malekpour, Roshan G. Ragel, Tuo Li, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
Hardware Trojan Mitigation in Pipelined MPSoCs. 6:1-6:27 - Renjian Pan, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Analog/RF Post-silicon Tuning via Bayesian Optimization. 7:1-7:17 - Qi Xu, Hao Geng, Song Chen, Bei Yu, Feng Wu:
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC. 8:1-8:19 - Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA. 9:1-9:26 - Pushpita Roy, Ansuman Banerjee, Robert Wille, Bhargab B. Bhattacharya:
Harnessing the Granularity of Micro-Electrode-Dot-Array Architectures for Optimizing Droplet Routing in Biochips. 10:1-10:37 - Amirhossein Esmaili, Mahdi Nazemi, Massoud Pedram:
Energy-aware Scheduling of Task Graphs with Imprecise Computations and End-to-end Deadlines. 11:1-11:21 - Hongfei Wang, Jianwen Li, Kun He:
Hierarchical Ensemble Reduction and Learning for Resource-constrained Computing. 12:1-12:21
Volume 25, Number 2, March 2020
- Tien-Hung Tseng, Chung-Han Chou, Kai-Chiang Wu:
Making Aging Useful by Recycling Aging-induced Clock Skew. 13:1-13:24 - Valentina Richthammer, Fabian Fassnacht, Michael Glaß:
Search-space Decomposition for System-level Design Space Exploration of Embedded Systems. 14:1-14:32 - Xu He, Yu Deng, Shizhe Zhou, Rui Li, Yao Wang, Yang Guo:
Lithography Hotspot Detection with FFT-based Feature Extraction and Imbalanced Learning Rate. 15:1-15:21 - Ramy N. Tadros, Peter A. Beerel:
A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures. 16:1-16:28 - Tung-Che Liang
Secure Assay Execution on MEDA Biochips to Thwart Attacks Using Real-Time Sensing. 17:1-17:25 - Irith Pomeranz:
Target Faults for Test Compaction Based on Multicycle Tests. 18:1-18:14 - Brooks Olney, Robert Karam:
Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure. 19:1-19:22 - Yajun Yang, Zhang Chen, Yuan Liu, Tsung-Yi Ho
How Secure Is Split Manufacturing in Preventing Hardware Trojan? 20:1-20:23 - Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. 21:1-21:23 - Jin-Tai Yan
Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment. 22:1-22:21 - Shi Sha
On Fundamental Principles for Thermal-Aware Design on Periodic Real-Time Multi-Core Systems. 23:1-23:23
Volume 25, Number 3, May 2020
- Arijit Nath, Sukarn Agarwal
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System. 24:1-24:32 - Nishant Kamal, Ankur Gupta
Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids. 25:1-25:34 - Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation. 26:1-26:27 - Huili Chen, Seetal Potluri, Farinaz Koushanfar
Security of Microfluidic Biochip: Practical Attacks and Countermeasures. 27:1-27:29 - Sumit K. Mandal, Ganapati Bhat, Janardhan Rao Doppa, Partha Pratim Pande, Ümit Y. Ogras
An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms. 28:1-28:26 - Mengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty
Algorithmic Fault Detection for RRAM-based Matrix Operations. 29:1-29:31
Volume 25, Number 4, September 2020
- Yoonah Paik, Seon Wook Kim, Dongha Jung, Minseong Kim:
Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead. 30:1-30:23 - Rajib Lochan Jana, Soumyajit Dey, Pallab Dasgupta:
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation. 31:1-3:33 - Urbi Chatterjee, Soumi Chatterjee, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT. 32:1-32:21 - Arunkumar Vijayan, Mehdi B. Tahoori, Krishnendu Chakrabarty
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection. 33:1-33:23 - Qutaiba Alasad, Jiann-Shuin Yuan, Pramod Subramanyan:
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks. 34:1-34:31 - Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte
Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation. 35:1-35:22
Volume 25, Number 5, October 2020
Special Issue on Machine Learning
- Jörg Henkel, Hussam Amrouch, Marilyn Wolf:
Introduction to the Special Issue on Machine Learning for CAD. 36:1-36:2 - Hannah Szentimrey, Abeer Y. Al-Hyari, Jérémy Foxcroft, Timothy Martin, David Noel, Gary William Grewal, Shawki Areibi:
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement. 37:1-37:25 - Mengyun Liu, Renjian Pan, Fangming Ye, Xin Li, Krishnendu Chakrabarty
Fine-grained Adaptive Testing Based on Quality Prediction. 38:1-38:25 - Felix Last
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks. 39:1-39:19 - Mehran Goli
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques. 40:1-40:28 - Yehya Nasser, Carlo Sau, Jean-Christophe Prévotet, Tiziana Fanni
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning. 41:1-41:29 - Sukanta Dey
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network. 42:1-42:29 - Qicheng Huang, Chenlei Fang, Soumya Mittal
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. 43:1-43:20 - Yong Hu, Marcel Mettler
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. 44:1-44:27 - Yi Wang, Paul D. Franzon
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration. 45:1-45:21 - Anthony Agnesina
Improving FPGA-Based Logic Emulation Systems through Machine Learning. 46:1-46:20 - Nektar Xama
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations. 47:1-47:27 - Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan
Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. 48:1-48:31
Volume 25, Number 6, October 2020
- X. Sharon Hu
Editorial: A Message from the New Editor-in-Chief. 49e:1-49e:2 - Mohammad Torabi, Lihong Zhang:
LDE-aware Analog Layout Migration with OPC-inclusive Routing. 49:1-49:22 - Chenlin Ma, Yi Wang
MNFTL: An Efficient Flash Translation Layer for MLC NAND Flash Memory. 50:1-50:19 - Christakis Lezos, Grigoris Dimitroulakos, Ioannis Latifis, Konstantinos Masselos:
A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis. 51:1-51:26 - Jingweijia Tan
Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity. 52:1-52:18 - Subodha Charles, Prabhat Mishra
Reconfigurable Network-on-Chip Security Architecture. 53:1-53:25 - Shilpa Pendyala, Sheikh Ariful Islam
Interval Arithmetic and Self-Similarity Based RTL Input Vector Control for Datapath Leakage Minimization. 54:1-54:26 - Hao-Yu Chi, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Wire Load Oriented Analog Routing with Matching Constraints. 55:1-55:26
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