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34th VLSI Design 2021: Guwahati, India
- 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021. IEEE 2021, ISBN 978-1-6654-4087-5
- Shubhankar Suman Singh, Smruti R. Sarangi:
ISAMod: A Tool for Designing ASIPs by Comparing Different ISAs. 1-6 - Shyamali Mitra, Debojyoti Banerjee, Mrinal K. Naskar:
A Low Latency Stochastic Square Root Circuit. 7-12 - Anish Reghunath, Mihir Mody, Hetul Sanghvi, Ankur:
Novel Census Transform Hardware IP. 13-16 - Vivek Tyagi, Shivam Kalla, Vikas Rana:
Negative Voltage Generator and Current DAC Based Regulator For Flash Memory. 17-22 - Vivek Tyagi, Vikas Rana:
Adaptive Forward Body Bias Voltage Generator. 23-28 - Chinmaye Ramamurthy, Chetan D. Parikh
, Subhajit Sen:
Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients. 29-34 - Arun Mohan, Saroj Mondal:
Challenges in Adoption of RF to DC Converter for Micro-Scale RF Energy Harvesting Systems. 35-40 - Shekhar Suman Borah, Ankur Singh, Mourina Ghosh
A Novel Low-Power Electronically Tunable Higher-Order Quadrature Oscillator using CDBA. 41-46 - Debjyoti Bhattacharjee
In-memory realization of SHA-2 using ReVAMP architecture. 47-53 - P. S. Babu, Snehashri Sivaraman, Deepa N. Sarma, Tripti S. Warrier
Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V. 54-59 - Pooja S. Shanbhag, Sujata Kotabagi, Priyanka Buduru, Pruthvi Benagi, S. Suma, Shraddha H:
Ring Oscillator with Improved Design. 60-64 - Hameedah Sultan, Smruti R. Sarangi:
Variability-Aware Thermal Simulation using CNNs. 65-70 - Noble Sebastian, Chavva Subbareddy, Immanuel Raja
A 3.55 dB NF Ultra-Compact Noise-Optimized LNA for 5G mm-Wave Bands in 65nm CMOS. 71-75 - Feraj Husain, Belal Iqbal, Anuj Grover
A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology. 76-81 - Sumanta Pyne:
Instruction Controlled In-memory Sorting on Memristor Crossbars. 82-87 - Katsuhiro Ichikawa, Shigeru Yamashita
A Multiply Accumulator for Stochastic Numbers Without Scaling Errors. 88-93 - Arjun Kumar, Akhilesh Rawat, Brajesh Rawat:
Prospects of Two-dimensional Material-based Field-Effect Transistors for Analog/RF Applications. 94-98 - Prasad Kulkarni, Sahil Garg, Shubhi Agrawal, Maryam Shojaei Baghini:
Low Power Extended Range Multi-Modulus Divider Using True-Single-Phase-Clock Logic. 99-104 - Anirban Barman, Ashis Maity
DC-DC Converter for Powering Micro-system Load in Energy Harvesting Front-ends. 105-110 - Arghadip Das
HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks. 111-116 - Niraj Kumar, Arijit Mondal:
Online Optimization of Energy Consumption and Makespan for Active Replication based Scheduling Approaches for Real-time Systems. 117-122 - Mohammad Ebrahimabadi, Mohamed F. Younis
A Novel Modeling-Attack Resilient Arbiter-PUF Design. 123-128 - Sairam Sri Vatsavai, Ishan G. Thakkar:
Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing. 129-134 - Dharmaray Nedalgi, Saroja V. Siddamal:
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone. 135-138 - Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das:
Minimization of Switching Activity of Graphene Based Circuits. 139-144 - Krashna Nand Mishra, Yogeshbhai Vallabhbhai Patel:
Creating Fastest Self timing Reference Path for High Speed Memory Designs. 145-150 - Sriharsha Enjapuri, Deepesh Gujjar, Sandipan Sinha, Ramesh Halli, Manish Trivedi:
A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications. 151-156 - Ayushparth Sharma, Kusum Lata:
Reconfigurable HW-SW Co-design Platform for Lung Cancer Detection and Classification. 157-162 - Richa Sharma
A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN. 163-168 - Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. 169-174 - B. S. Ajay, Madhav Rao:
Binary neural network based real time emotion detection on an edge computing device to detect passenger anomaly. 175-180 - Sudipa Mandal, Krushna Gaurkar, Pallab Dasgupta, Aritra Hazra:
An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors. 181-186 - Diksha Moolchandani, Geesara Prathap
Game Theory-Based Parameter-Tuning for Path Planning of UAVs. 187-192 - Kumari Anjali, Shubham Saha, Anuj Grover
Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders. 193-198 - Shashank Banchhor, Nitanshu Chauhan, Aditya Doneria, Bulusu Anand:
Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect. 199-203 - Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine:
PositGen-A Verification Suite for Posit Arithmetic. 204-209 - P. Saravanan
Hardware Accelerator for Dual Standard Deblocking Filter. 210-215 - Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta:
A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. 216-221 - Miryala Chandra Shekar, Sandeep Goyal, Shalabh Gupta:
A 27S/32S DC-balanced line coding scheme for PAM-4 signaling. 222-227 - Rounak Chatterjee, Souradeep Chowdhury, Soham Mondal, Arnab Raha, Janet Paluh, Amitava Mukherjee:
PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry. 228-233 - Prasenjit Saha, Hema Sai Kalluru, Zia Abbas
Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence. 234-239 - Remya Ramakrishnan, Aditya K. V. Dev, Darshik A. S, Renuka Chinchwadkar, Madhura Purnaprajna:
Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis. 240-245 - Sumit Sharma
Optical Waveguide Channel Routing with Reduced Bend-Loss for Photonic Integrated Circuits. 246-251 - Sanmitra Bharat Naik, Siddharth R. K.
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. 252-257 - Pandy Kalimuthu, Kanad Basu, Benjamin Carrión Schäfer:
Efficient Hierarchical Post-Silicon Validation and Debug. 258-263 - Krishnendu Guha, Amlan Chakrabarti, Krishna Paul, Biswadeep Chatterjee:
Criticality based Reduction of Security Costs in a FPGA based Cloud Computing Farm. 264-269 - Farhad Merchant, Dominik Sisejkovic
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. 270-275 - Ihsen Alouani
An Investigation on Inherent Robustness of Posit Data Representation. 276-281 - Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine:
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. 282-287 - Aniali Agrawal, Anand Singh, Ankit Gola, Hameedah Sultan, Smruti R. Sarangi:
A Fast Compact Thermal Model For Smart Phones. 288-293 - Javed S. Gaggatur:
A 1.8 - 6.3 GHz Quadrature Ring VCO-based Fast-settling PLL for Wireline I/O in 55nm CMOS. 294-298 - Vasudevan Madampu Suryasarman, Santosh Biswas, Aryabartta Sahu:
Automated Low-Cost SBST Optimization Techniques for Processor Testing. 299-304 - Nisarga Ramesh, Javed S. Gaggatur:
A 0.6 V, 2nd order low-pass Gm-C filter using CMOS inverter-based tunable OTA with 1.114 GHz cut-off frequency in 90nm CMOS technology. 305-309 - Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman:
Neural Network based Indirect Estimation of Functional Parameters of Amplifier by extracting features from Wavelet Transform. 310-315 - Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. 316-321 - Masoud Shahshahani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Dinesh Bhatia
An Automated Tool for Implementing Deep Neural Networks on FPGA. 322-327 - Arnab Raha, Sang Kyun Kim, Deepak Mathaikutty, Guruguhanathan Venkataramanan, Debabrata Mohapatra, Raymond Sung, Cormac Brick, Gautham N. Chinya:
Design Considerations for Edge Neural Network Accelerators: An Industry Perspective. 328-333
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