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6th VLSI Design 1993: Bombay, India
- Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993. IEEE Computer Society 1993, ISBN 0-8186-3180-5
Keynote Address
- Osamu Karatsu:
On the History and Future Detecion of VLSI Design and CAD - Japanese Perspective. 3-4
1. Logic Synthesis
- Vinaya Kumar Singh, Ajit Arvind Diwan:
A Heuristic for Decomposition in Multi-Level Logic Optimization. 5-8 - Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose:
Combining State Assignment with PLA Folding. 9-14 - Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. 15-20 - Alexandre Yakovlev:
Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs. 21-24
2. VLSI Algorithms
- Mario Kovac, N. Ranganathan, M. Varanasi:
SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. 25-30 - Chowdhury S. Rahman, Mi Lu:
A Partition Approach to Find the Length of the Longest Common Subsequence. 31-36 - Rachid Bouraoui, Alain Guyot, G. Walker:
Design of an On-Line Euclidean Processor. 37-40 - Raghu Sastry, N. Ranganathan, Horst Bunke:
Hardware Algorithms for Polygon Matching. 41-44
3. Design for Testability
- Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni:
Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. 45-50 - Yves Bertrand, Frédéric Bancel, Michel Renovell:
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. 51-54 - Amitava Majumdar, Sarma Sastry:
Statistical Analysis of Controllability. 55-60 - Wen-Ben Jone, Sunil R. Das:
CACOP - A Random Pattern Testability Analyzer. 61-64 - B. Krieger:
PLATO: A Tool for Computation of Exact Signal Probabilities. 65-68 - Irith Pomeranz, Sudhakar M. Reddy:
On the Generation of Weights for Weighted Pseudo Random Testing. 69-72
4. Physical Design
- Suhail Ahmed, T. V. Nagesh, Ramoji Rao, B. Naveen, P. K. Fangaria, K. S. Raghunathan:
FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview. 73-79 - Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta:
NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. 80-83 - Ed P. Huijbregts, Jochen A. G. Jess:
A Multiple Terminal Net Routing Algorithm Using Failure Prediction. 84-89 - Joon Shik Lim, S. Sitharama Iyengar, Si-Qing Zheng:
Euclidean Shortest Path Problem with Rectilinear Obstacles. 90-93 - Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani:
On Optimum Cell Models for Over-the-Cell Routing. 94-99 - Mahesh Mehendale, Kaushik Roy:
Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. 100-103
5. Poster Introductions
- P. R. Suresh Kumar, Mandyam-Komar Srinivas, James Jacob:
Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation. 104 - S. Raman, M. M. Hasan:
A PLA-Based FSM Design Technique. 105-106 - Dipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri:
Synthesis of Self-Checking Sequential Machines Using Cellular Automata. 107 - Himanshu S. Mazumdar:
A Multilayered Feed Forward Neural Network Suitable for VLSI Implementation. 108 - Sandip Das, Bhargab B. Bhattacharya:
Via Minimization in Channel Routing by Layout Modification. 109-110 - C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer:
High Level Design Experiences with IDEAS. 110 - P. Marimuthu, K. S. Raghunathan:
BEST: Bond Editor and Test Vector Translator. 111 - Biswadip Mitra, Parimal Pal Chaudhuri:
A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead. 112 - Jason Cong, Moazzem Hossain, Naveed A. Sherwani:
A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. 113
6. VLSI Education
- Kanti Prasad, Aditya Goel:
Preparing Engineers to Meet the Challenges of the 21st Century Through VLSI Education. 114-117
7. Testing
- W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana:
Use of Storage Elements as Primitives for Modelling Faults in Synchronous Sequential Circuits. 118-123 - Didier Crestani, A. Aguila, L. Eudeline, M.-H. Gentil, Christian Durante:
A Hierarchical Test Generation Using High Level Primitives. 124-127 - Bernd Becker, Rolf Krieger:
FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits. 128-131 - M. Srinivas, Lalit M. Patnaik:
A Simulation-Based Test Generation Scheme Using Genetic Algorithms. 132-135 - Rochit Rajsuman, David A. Penry:
Coverage of Bridging Faults by Random Testing in IDDQ Test Environment. 136-139 - Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin:
Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. 140-143 - Choong Gun Oh, Hee Yong Youn, Vijay K. Raj:
Algorithm-Based Concurrent Error Detection for FFT Networks. 144-147
8. Digital Signal Processing
- Lih-Gwo Jeng, Liang-Gee Chen:
Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding. 148-153 - Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu:
Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. 154-159 - Luigi Dadda:
A Simplified High Speed Parallel Input Convolver. 160-165 - V. Visvanathan, Nibedita Mohanty, S. Ramanathan:
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. 166-171 - Arjun Rajagopal, Belli Kuttanna, Balaji Janakiraman, Rajarshi Mukherjee, Joy Shetler:
A Reconfigurable Arithmetic Processor. 172-175 - S. Ramanathan, Nibedita Mohanty, V. Visvanathan:
A Methodology for Generating Application Specific Tree Multipliers. 176-179
9. High Level Synthesis
- Hyuk-Jae Jang, Barry M. Pangrle:
GB: A New Grid-Based Binding Approach for High-Level Synthesis. 180-185 - Ahmed Hemani:
Self-Organization and its Application to Binding. 186-191 - Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji:
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. 192-197 - Haigeng Wang, Nikil D. Dutt
, Alexandru Nicolau:
Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies. 198-201 - Byung Wook Jeon, Chidchanok Lursinsap:
MS3: Micro-Rollback and Self-Recovery System Synthesis. 202-207
10. Module Generators
- Khushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy:
Genetic Beam Search for Gate Matrix Layout. 208-213 - Akhilesh Tyagi:
A Module Generator Development Environment: Area Estimation and Design-Space Exploration Encapsulation. 214-217 - G. Pannerselvam, A. Sarkar, Subir Bandyopadhyay, Graham A. Jullien:
Area Efficient VLSI Design with Cells of Controllable Complexity. 218-221 - Rajeev Govindan, Michael A. Langston, Siddharthan Ramachandramurthi:
A Practical Approach to Layout Optimization. 222-225 - Bjarne Hald, Jan Madsen:
Performance Aspects of Gate Matrix Layout. 226-229 - Aditya Agrawal, P. V. Srinivas, Gade Sreenivas, Uttiya Dasgupta:
LATCHECK: A Latchup Checker for VLSI Layouts. 230-235
11. Parallel CAD
- S. Bapat, James P. Cohoon:
A Parallel VLSI Circuit Layout Methodology. 236-241 - Krishnaiyan Thulasiraman, Prasad R. Chalasani, Parimala Thulasiraman, M. A. Comeau:
Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire Balancing. 242-245 - Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal:
Architecture of a Min-Max Simulator on MARS. 246-249
12. VLSI Architecture
- Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
A Massively Parallel, Micro-Grained VLSI Architecture. 250-255 - Pradip Bose, John-David Wellman:
MIPS-Driven Early Design and Analysis of VLSI CPU Chips. 256-259 - Anna Antola, Alberto Avai, Luca Breveglieri, Andrea Paparella:
Modular Design Methodologies for Image Processing Architectures. 260-263
13. Panel
- Sunil D. Sherlekar:
Export of VLSI Design and CAD: Present and Future. VLSI Design 1993: 264
14. Delay Fault Testing
- Ankan K. Pramanick, Sudhakar M. Reddy:
On Unified Delay Fault Testing. 265-268 - Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
A Path Delay Fault Simulator for Sequential Circuits. 269-274 - Sandeep Bhatia, Niraj K. Jha:
Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. 275-280 - Sukumar Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy:
Delay Fault Test Generation with Cellular Automata. 281-286
15. CAD Frameworks
- K. S. V. Gopalarao, Uttiya Dasgupta, Rajeev Jain, Duane S. Boning, Purnendu K. Mozumder, V. Chandramouli:
An Integrated Technology CAD System for Process and Device Designers. 287-292 - Peter M. Kist, N. Simon, Mattie N. Sim, E. Marks, Kees Schot, A. Sarotama:
A Mechanism for Fine-Grain Concurrent Sharing of Design Data Among CAD Tools. 293-298 - M. V. Rao, M. Balakrishnan, Anshul Kumar:
DESSERT: Design Space Exploration of RT Level Components. 299-304 - Klaus D. Müller-Glaser, Jürgen Bortolazzi, Yankin Tanurhan, Johannes Ernst:
CAE in Requirements Definition and Specification for Complex Microelectronic Systems. 305-310
16. RTL and Logic Design
- Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith:
Optimizations for Behavioral/RTL Simulation. 311-316 - Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga:
A Shared Memory Parallel Algorithm for Logic Synthesis. 317-322 - Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Minimization of Logic Functions Using Essential Signature Sets. 323-328 - Olivier Coudert, Jean Christophe Madre:
Towards a Symbolic Logic Minimization Algorithm. 329-334 - Susanta Misra, Biswadip Mitra, Parimal Pal Chaudhuri:
A Novel Scheme for Synthesis of Easily Testable Finite State Machines Using Cellular Automata. 335-340
17. Circuit Design
- Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan:
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. 341-346 - Dinesh Somasekhar, V. Visvanathan:
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. 347-350 - Joydeep Ghosh, Nari Krishnamurthy:
Fault-Tolerant Arbitration in Multichip Crossbar Switches. 351-356 - João C. Vital, José E. Franca:
High-Speed A/D-D/A Conversion System with Flexible Testing Capabilities. 357-362 - M. Shamanna, Sterling R. Whitaker:
A Carry Select Adder with Conflict Free Bypass Circuit. 363-366 - Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
New CMOS Structures for the Synthesis of Dominant Functions. 367-370
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