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15th PATMOS 2005: Leuven, Belgium
- Vassilis Paliouras, Johan Vounckx, Diederik Verkest:
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings. Lecture Notes in Computer Science 3728, Springer 2005, ISBN 3-540-29013-3
Low-Power Processors
- Fernando Castro
, Daniel Chaver
A Power-Efficient and Scalable Load-Store Queue Design. 1-9 - David Rios-Arambula, Aurélien Buhrig, Marc Renaudin:
Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. 10-18 - Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat:
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. 19-29 - Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Dynamic Instruction Cascading on GALS Microprocessors. 30-39 - Guadalupe Miñana, Oscar Garnica
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. 40-48
Code Optimization for Low-Power
- Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Ricardo Massa Ferreira Lima, Angelo Ribeiro, César A. L. de Oliveira, Adilson Arcoverde, Raimundo S. Barreto, Eduardo Tavares, Leonardo Amorim:
A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net. 49-58 - Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis:
Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory. 59-68 - José Manuel Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, Jose Manuel Mendias:
Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems. 69-78 - Huizhan Yi, Xuejun Yang:
Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications. 79-88
High-Level Design
- Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor:
Systematic Preprocessing of Data Dependent Constructs for Embedded Systems. 89-98 - Ali Manzak
Temperature Aware Datapath Scheduling. 99-106 - Bert Geelen, Gauthier Lafruit, Vissarion Ferentinos, Rudy Lauwereins, Diederik Verkest:
Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform. 107-116 - Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris
Improving the Memory Bandwidth Utilization Using Loop Transformations. 117-126 - Amjad Mohsen, Richard Hofmann:
Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures. 127-136
Telecommunications and Signal Processing
- Mustafa Aktan, Günhan Dündar
Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming. 137-145 - Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel:
A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction. 146-155 - Hyun-Ho Kim, Jung Hee Kim, Yong-hyeog Kang, Young Ik Eom:
An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments. 156-165 - Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon:
Energy-Aware System-on-Chip for 5 GHz Wireless LANs. 166-176 - Theodoros Giannopoulos, Vassilis Paliouras
Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction. 177-186
Low-Power Circuits
- Josep Rius, José Pineda de Gyvez, Maurice Meijer:
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. 187-196 - Jean-Félix Perotto, Stefan Cserveny:
Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques. 197-206 - Alexis De Vos, Yvan Van Rentergem:
Power Consumption in Reversible Logic Addressed by a Ramp Voltage. 207-216 - Yuanlin Lu, Vishwani D. Agrawal:
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. 217-226 - Pankaj Golani, Peter A. Beerel:
Back Annotation in High Speed Asynchronous Design. 227-236
System-on-Chip Design
- Tajana Simunic, Kresimir Mihic, Giovanni De Micheli:
Optimization of Reliability and Power Consumption in Systems on a Chip. 237-246 - Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. 247-256 - Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. 257-266 - Mariagrazia Graziano, Cristiano Forzan, Davide Pandini:
Power Supply Selective Mapping for Accurate Timing Analysis. 267-276
Busses and Interconnections
- Roshan Weerasekera
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. 277-285 - Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov
PSK Signalling on NoC Buses. 286-296 - Ashutosh Chakraborty, Enrico Macii, Massimo Poncino:
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. 297-307 - Giorgos Dimitrakopoulos, Dimitris Nikolos:
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. 308-317 - Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Efficient Simulation of Power/Ground Networks with Package and Vias. 318-328
Modeling
- Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo:
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. 329-336 - Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. 337-347 - José Luis Rosselló, Sebastià A. Bota, Jaume Segura
Compact Static Power Model of Complex CMOS Gates. 348-354 - Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. 355-363 - Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark:
Statistical Critical Path Analysis Considering Correlations. 364-373
Design Automation
- Didier Van Reeth, Georges G. E. Gielen:
A CAD Platform for Sensor Interfaces in Low-Power Applications. 374-381 - Eduardo Tavares, Raimundo S. Barreto, Paulo Romero Martins Maciel, Meuse N. Oliveira Jr., Adilson Arcoverde, Gabriel Alves, Ricardo Massa Ferreira Lima, Leonardo Barros, Arthur Bessa:
An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints. 382-392 - Miodrag Vujkovic, David Wadkins, Carl Sechen:
Efficient Post-layout Power-Delay Curve Generation. 393-403 - Radu Zlatanovici, Borivoje Nikolic
Power - Performance Optimization for Custom Digital Circuits. 404-414 - Siobhán Launders, Colin Doyle, Wesley Cooper:
Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs. 415-424
Low-Power Techniques
- Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa
Logic-Level Fast Current Simulation for Digital CMOS Circuits. 425-435 - Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. 436-445 - Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. 446-455 - Ireneusz Brzozowski, Andrzej Kos:
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes. 456-465
Memory and Register Files
- Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino:
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. 466-476 - Prassanna Sithambaram, Alberto Macii
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs. 477-487 - Armin Wellig, Julien Zory:
Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology. 488-497 - Shadi T. Khasawneh, Kanad Ghose:
An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers. 498-507 - William R. Roberts, Dimitrios Velenis:
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. 508-517
Poster Session 1: Applications
- Konstantina Karagianni, Vassilis Paliouras
Low-Power Aspects of Nonlinear Signal Processing. 518-527 - Vasily G. Moshnyaga, Eiji Morikawa:
Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring. 528-539 - Nabil Badereddine, Patrick Girard, Arnaud Virazel
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. 540-549 - François Macé, François-Xavier Standaert
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. 550-560 - Miguel Casas-Sanchez, Jose Rizo-Morente, Chris J. Bleakley:
Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSP. 561-570 - Alin Razafindraibe, Michel Robert
A Method to Design Compact Dual-rail Asynchronous Primitives. 571-580 - Eckhard Grass, Frank Winkler, Milos Krstic
Enhanced GALS Techniques for Datapath Applications. 581-590 - Haralambos Michail, Athanasios Kakarountas, George N. Selimis, Costas E. Goutis:
Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. 591-600
Poster Session 2: Digital Circuits
- Babak Salamat, Amirali Baniasadi:
Area-Aware Pipeline Gating for Embedded Processors. 601-608 - Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Fast Low-Power 64-Bit Modular Hybrid Adder. 609-617 - Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard:
Speed Indicators for Circuit Optimization. 618-628 - Francisco de Toro, Raúl Jiménez, Manuel Sanchez-Raya
Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms. 629-637 - Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel:
Power-Clock Gating in Adiabatic Logic Circuits. 638-646 - Yijun Liu, Stephen B. Furber
The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. 647-656 - Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. 657-665 - Francisco-Javier Veredas, Jordi Carrabina:
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. 666-673
Poster Session 3: Analog and Physical Design
- Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele:
The Optimal Wire Order for Low Power CMOS. 674-683 - Bécharia Nadji:
Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water. 684-692 - B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
Temperature Dependency in UDSM Process. 693-703 - Howard Chen, Louis Hsu:
Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System. 704-713 - Hamid Reza Sadr M. N:
A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor. 714-723 - Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. 724-732
Special Session: Digital Hearing Aids: Challenges and Solutions for Ultra Low Power
- Wolfgang Nebel, Bärbel Mertsching, Birger Kollmeier:
Digital Hearing Aids: Challenges and Solutions for Ultra Low Power. 733 - Thomas Rohdenburg, Volker Hohmann, Birger Kollmeier:
Tutorial Hearing Aid Algorithms. 734 - Arne Schulz, Wolfgang Nebel:
Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids. 735-736 - Thomas Eisenbach, Bärbel Mertsching, Nikolaus Voß, Frank Schmidtmeier:
Optimization of Modules for Digital Audio Processing. 737-746
Invited Talks
- Jan M. Rabaey:
Traveling the Wild Frontier of Ultra Low-Power Design. 747 - Sung-Bae Park:
DLV (Deep Low Voltage): Circuits and Devices. 748 - Magdy A. Bayoumi:
Wireless Sensor Networks: A New Life Paradigm. 749 - Odysseas G. Koufopavlou, George N. Selimis, Nicolas Sklavos, Paris Kitsos
Cryptography: Circuits and Systems Approach. 750
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