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18th ISQED 2017: Santa Clara, California, USA
- 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, CA, USA, March 14-15, 2017. IEEE 2017, ISBN 978-1-5090-5404-6
Session 1A: Cognitive Computing on Conventional and Emerging Platforms
- Hongyu An, M. Amimul Ehsan, Zhen Zhou, Yang Yi:
Electrical modeling and analysis of 3D synaptic array using vertical RRAM structure. 1-6 - Lita Yang, Boris Murmann
:
SRAM voltage scaling for energy-efficient convolutional neural networks. 7-12 - Mohammed Alawad
Stochastic-based multi-stage streaming realization of deep convolutional neural network. 13-18 - Tao Liu, Wujie Wen:
A fast and ultra low power time-based spiking neuromorphic architecture for embedded applications. 19-22
Session 1B: Design Opportunities and Challenges in Non-Volatile Technologies
- Wei-Hao Chen, Win-San Khwa, Jun-Yi Li, Wei-Yu Lin, Huan-Ting Lin, Yongpan Liu, Yu Wang, Huaqiang Wu, Huazhong Yang, Meng-Fan Chang:
Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing. 23-28 - Sumeet Kumar Gupta, Danni Wang, Sumitha George, Ahmedullah Aziz
Harnessing ferroelectrics for non-volatile memories and logic. 29-34 - Insik Yoon, Arijit Raychowdhury:
Test challenges in embedded STT-MRAM arrays. 35-38 - Kaisheng Ma
Evaluating tradeoffs in granularity and overheads in supporting nonvolatile execution semantics. 39-44
Session 1C: A Look into Future of Circuits, Interconnects and Memory with Emerging Technology
- Shaloo Rakheja:
Communication limits of on-chip graphene plasmonic interconnects. 45-51 - Navid Khoshavi, Soheil Salehi, Ronald F. DeMara
Variation-immune resistive Non-Volatile Memory using self-organized sub-bank circuit designs. 52-57 - Lei Zhao, Lei Jiang, Youtao Zhang, Nong Xiao, Jun Yang:
Constructing fast and energy efficient 1TnR based ReRAM crossbar memory. 58-64
Session 2A: Low-Power/Fault-Tolerant Memories Using Scaled Technologies
- Xin Fan, Jan Stuijt, Rui Wang, Bo Liu, Tobias Gemmeke
Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations. 65-70 - Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
Tunnel FET based ultra-low-leakage compact 2T1C SRAM. 71-75 - Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao:
Low redundancy matrix-based codes for adjacent error correction with parity sharing. 76-80 - Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi:
0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives. 81-86
Session 2B: Design for Manufacturability and Reliability
- Stephen K. Heinrich-Barna, Clyde Dunn, Doug Verret:
Low temperature endurance failures on flash memory. 87-92 - Samuel Pagliarini
Virtual characterization for exhaustive DFM evaluation of logic cell libraries. 93-98 - J. Andres Torres, Germain Fenger, Daman Khaira, Yuansheng Ma, Yuri Granik, Chris Kapral, Joydeep Mitra, Polina Krasnova, Dehia Ait-Ferhat:
Overview and development of EDA tools for integration of DSA into patterning solutions. 99-103 - Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. 104-110
Session P: Posters
- Subrata Das, Debesh Kumar Das:
A technique to construct global routing trees for graphene nanoribbon (GNR). 111-118 - Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Maria Malik, Ali Chehab
Regularized logistic regression for fast importance sampling based SRAM yield analysis. 119-124 - Jeferson José Baqueta
Binary adder circuit design using emerging MIGFET devices. 125-130 - Sungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg:
A case for standard-cell based RAMs in highly-ported superscalar processor structures. 131-137 - Chenyuan Zhao, Jialing Li, Hongyu An
Energy efficient analog spiking temporal encoder with verification and recovery scheme for neuromorphic computing systems. 138-143 - Maha Beheiry, Hassan Mostafa
3D-NOCET: A tool for implementing 3D-NoCs based on the Direct-Elevator algorithm. 144-148 - Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark:
Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. 149-154 - Alexander Holst, Jae-Won Jang, Swaroop Ghosh:
Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory. 155-160 - Chunhua Qi, Liyi Xiao, Mingxue Huo, Tianqi Wang, Rongsheng Zhang, Xuebing Cao:
A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications. 161-165 - Amir Masoud Gharehbaghi
A new approach for selecting inputs of logic functions during debug. 166-173 - Hongjia Li, Ji Li, Wang Yao, Shahin Nazarian, Xue Lin, Yanzhi Wang:
Fast and energy-aware resource provisioning and task scheduling for cloud systems. 174-179 - Mehmet Meric Isgenc, Samuel Pagliarini
Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs. 180-185 - Harry Kalargaris, Yi-Chung Chen, Vasilis F. Pavlidis:
STA compatible backend design flow for TSV-based 3-D ICs. 186-190 - Sungyoul Seo, Hyeonchan Lim, Soyeon Kang, Sungho Kang:
Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. 191-195 - Md. Nazmul Islam
Determining proximal geolocation of IoT edge devices via covert channel. 196-202
Session 3A: Power and Timing Optimization
- Daijoon Hyun, Wachirawit Ponghiran, Youngsoo Shin:
Clock tree optimization through selective airgap insertion. 203-208 - Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens:
An analytical model for interdependent setup/hold-time characterization of flip-flops. 209-214 - Sam C. Lo, Taylor T. Lee, Aaron J. Barker:
High sigma statistical hold time analysis in FinFET sequential circuits. 215-220 - Vijay Kiran Kalyanam, Peter G. Sassone, Jacob A. Abraham:
Power prediction of embedded scalar and vector processor: Challenges and solutions. 221-228 - Shantanu Dutt, Ouwen Shi:
Power-delay product based resource library construction for effective power optimization in HLS. 229-236
Session 3B: Hardware Security
- Zihan Pang, Jiliang Zhang, Qiang Zhou, Shuqian Gong, Xu Qian, Bin Tang:
Crossover Ring Oscillator PUF. 237-243 - Lawrence T. Clark, James Adams, Keith E. Holbert:
Integrated circuit identification and true random numbers using 1.5-transistor flash memory. 244-249 - Deepakreddy Vontela, Swaroop Ghosh:
Methodologies to exploit ATPG tools for de-camouflaging. 250-256 - Xiaoming Chen, Qiaoyi Liu, Yu Wang, Qiang Xu
Low-overhead implementation of logic encryption using gate replacement techniques. 257-263 - Xi Chen, Gang Qu, Aijiao Cui, Carson Dunbar:
Scan chain based IP fingerprint and identification. 264-270
Session 3C: Novel Reliability Solutions for 3D ICs
- Dongjin Lee, Sourav Das, Partha Pratim Pande:
Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture. 271-276 - Yiting Chen, Dae Hyun Kim:
A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits. 277-282 - Kaoru Furumi, Masashi Imai, Atsushi Kurokawa:
Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs. 283-288 - Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe:
High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC. 289-295 - Sameer Shekhar, Amit K. Jain, Pooja Nukala:
Data interface buffer compensation scheme for fast calibration. 296-300
Session 4A: Lightweight Security for Internet-of-Things: Attacks, Countermeasures and Efficient Implementations
- Ville Yli-Mäyry, Naofumi Homma, Takafumi Aoki:
Chosen-input side-channel analysis on unrolled light-weight cryptographic hardware. 301-306 - Jakub Breier
An electromagnetic fault injection sensor using Hogge phase-detector. 307-312 - Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang
FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability. 313-318 - Tim Güneysu
Towards lightweight Identity-Based Encryption for the post-quantum-secure Internet of Things. 319-324 - Debjyoti Bhattacharjee
SHA-3 implementation using ReRAM based in-memory computing architecture. 325-330
Session 4B: Design for Smart Sensors and Internet of Things
- Everton Luís Berz, Deivid Antunes Tesch, Fabiano Passuelo Hessel
A hybrid RFID and CV system for item-level localization of stationary objects. 331-336 - Wazir Singh
Energy efficient biopotential acquisition unit for wearable health monitoring applications. 337-341 - Leo Filippini
Wireless charge recovery system for implanted electroencephalography applications in mice. 342-345 - Mohsen Imani, Tajana Rosing:
CAP: Configurable resistive associative processor for near-data computing. 346-352
Session 4C: Innovative Energy Management for Modern Systems
- Ruturaj Pujari, Shaloo Rakheja:
Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures. 353-359 - Gustavo A. Chaparro-Baquero
Processor/memory Co-Scheduling using periodic resource server for real-time systems under peak temperature constraints. 360-366 - Ning Liu, Xue Lin, Yanzhi Wang:
Data center power management for regulation service using neural network-based power prediction. 367-372 - Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy
An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors. 373-378 - Scott Lerner, Baris Taskin:
Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. 379-384
Session 5A: Energy Efficient Logic Design Using Scaled Technologies
- Mohammad Saber Golanbari, Saman Kiamehr, Fabian Oboril, Anteneh Gebregiorgis, Mehdi Baradaran Tahoori:
Post-fabrication calibration of Near-Threshold circuits for energy efficiency. 385-390 - Shaahin Angizi
Composite spintronic accuracy-configurable adder for low power Digital Signal Processing. 391-396 - Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
Low latency divider using ensemble of moving average curves. 397-402 - Pravin Mane
Adder implementation in reconfigurable resistive switching crossbar. 403-408 - Abhijit Das, Joonsung Park:
High precision yet wide range on-chip oscillator with dual charge-discharge technique. 409-412
Session 5B: Synthesis and Reliability
- Chia-Chun Lin, Chiao-Wei Huang, Chun-Yao Wang, Yung-Chih Chen:
In&Out: Restructuring for threshold logic network optimization. 413-418 - Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita:
Systematic approximate logic optimization using don't care conditions. 419-425 - Shumpei Morita, Song Bian, Michihiro Shintani
Comparative study of path selection and objective function in replacing NBTI mitigation logic. 426-431 - Qinhao Wang, Yusuke Kimura, Masahiro Fujita:
Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs. 432-437
Session 5C: Verification and Test
- Qianqian Fan, Sachin S. Sapatnekar
Cost-quality trade-offs of approximate memory repair mechanisms for image data. 438-444 - Phaninder Alladi, Spyros Tragoudas:
Aging-aware critical paths for process related validation in the presence of NBTI. 445-448 - Hyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang:
Broadcast scan compression based on deterministic pattern generation algorithm. 449-453 - Jizhe Zhang, Sandeep K. Gupta:
Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging. 454-459 - Pranav Ashar, Vikas Sachdeva, Vinod Viswanath
Failures and verification solutions related to untimed paths in SOCs. 460-465
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