default search action
ISQED 2014: Santa Clara, California, USA
- Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014. IEEE 2014, ISBN 978-1-4799-3945-9
- Jacqueline Woods, Sridhar Iyengar, Amit Sinha, Subhasish Mitra, Stacy Cannady:
A new era of computing: Are you "ready now" to build a smarter and secured enterprise? 1
Session 1A: Memory Circuits and Systems
- Arijit Banerjee
, Mahmut E. Sinangil, John W. Poulton, C. Thomas Gray, Benton H. Calhoun:
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. 1-8 - Hu Chen, Sanghamitra Roy
Exploiting static and dynamic locality of timing errors in robust L1 cache design. 9-15 - Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. 16-23 - Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa:
40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. 24-31 - Peyman Pouyan, Esteve Amat
Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches. 32-38
Session 1B: Advanced Techniques for System-level Analysis
- Yao Li, Ramy Iskander, Marie-Minerve Louërat:
Modeling, design and verification platform using SystemC AMS. 39-46 - Chongxi Bao, Domenic Forte
On application of one-class SVM to reverse engineering-based hardware Trojan detection. 47-54 - Jarbas Silveira
Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation. 55-59 - Anirban Sengupta, Vipul Kumar Mishra
Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis. 60-67 - Saad Bin Nasir
Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators. 68-75
Session 1C: Network on a Chip and Multi-core Systems
- Tejasi Pimpalkhute, Sudeep Pasricha:
An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors. 76-83 - Alexandra Aguiar, Carlos Moratelli
Adding virtualization support in MIPS 4Kc-based MPSoCs. 84-90 - Shirish Bahirat, Sudeep Pasricha:
HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures. 91-98 - Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi
An analytical approach to system-level variation analysis and optimization for multi-core processor. 99-106 - Tianyi Wang, Ming Fan, Gang Quan
Heterogeneity exploration for peak temperature reduction on multi-core platforms. 107-114 - Prasanjeet Das, Sandeep K. Gupta:
Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations. 115-122 - Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger
Protection of Muller-Pipelines from transient faults. 123-131 - Eduardo Wächter
Runtime fault recovery protocol for NoC-based MPSoCs. 132-139 - Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Shih-Chieh Chang:
Concurrency-oriented SoC re-certification by reusing block-level test vectors. 140-147 - Kamran Rahmani, Prabhat Mishra
Efficient trace signal selection using augmentation and ILP techniques. 148-155 - Sudhi Proch, Prabhat Mishra
Directed test generation for hybrid systems. 156-162
Session 2B: Package and 3-D Integration
- Kyungsu Kang, Giovanni De Micheli, Seunghan Lee, Chong-Min Kyung:
Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache. 163-170 - Song Yao, Xiaoming Chen, Yu Wang
Efficient region-aware P/G TSV planning for 3D ICs. 171-178 - Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee:
3D-ICs with self-healing capability for thermal effects in RF circuits. 179-183 - Mir Mohammad Navidi, Gyung-Su Byun:
Comparative analysis of clock distribution networks for TSV-based 3D IC designs. 184-188 - Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
Delay and power optimization with TSV-aware 3D floorplanning. 189-196 - Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung:
Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors. 197-204
Session 2C: Manufacturing and Modeling Issues in Nanoscale CMOS
- Sabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab
Statistical methodology for modeling non-IID memory fails events. 205-211 - Wei Wang:
Automated Shmoo data analysis: A machine learning approach. 212-218 - Seong-I Lei, Chris Chu, Wai-Kei Mak:
Double patterning-aware detailed routing with mask usage balancing. 219-223 - Sharayu Jagtap, Sivaramakrishna Rudrapati, Shalabh Gupta:
Design of radiation hardened wide tuning range CMOS oscillators. 224-229 - Tomohiro Fujita, SinNyoung Kim, Hidetoshi Onodera:
Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model. 230-235 - Varadan Savulimedu Veeravalli, Andreas Steininger
Measuring SET pulsewidths in logic gates using digital infrastructure. 236-242
Session 3A: Low Voltage and Low Power Design Methodologies
- Yanqing Zhang, Benton H. Calhoun:
Fast, accurate variation-aware path timing computation for sub-threshold circuits. 243-248 - Xue Lin, Yanzhi Wang, Shahin Nazarian, Massoud Pedram:
An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes. 249-256 - Bo Liu, Maryam Ashouei, Tobias Gemmeke
Sub-threshold custom standard cell library validation. 257-262 - Kartikeya Bhardwaj, Pravin S. Mane
Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems. 263-269 - Mark Buckler, Wayne P. Burleson:
Predictive synchronization for DVFS-enabled multi-processor systems. 270-275
Session 3B: Systems Optimization
- Heesun Kim, Seungyun Sohn, Yoonjin Kim:
Ring-based sharing fabric for efficient pipelining of kernel-stream on CGRA-based multi-core architecture. 276-283 - Ming Fan, Qiushi Han, Gang Quan
Multi-core partitioned scheduling for fixed-priority periodic real-time tasks with enhanced RBound. 284-291 - Parag Kulkarni, Puneet Gupta
Minimizing clock domain crossing in Network on Chip interconnect. 292-299 - Andrew B. Kahng, Siddhartha Nath:
Optimal reliability-constrained overdrive frequency selection in multicore systems. 300-308 - Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
RTL datapath optimization using system-level transformations. 309-316 - Anup Shrivastava
Dual-sided doped memristor and it's SPICE modelling for improved electrical properties. 317-322 - Komal Singh, Chitrakant Sahu
Linearly separable pattern classification using memristive crossbar circuits. 323-329 - Makoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada
Low-power programmable-logic cell arrays using nonvolatile complementary atom switch. 330-334 - Mukta Singh Parihar
Volume accumulated double gate junctionless MOSFETs for low power logic technology applications. 335-340 - Xue Lin, Yanzhi Wang, Massoud Pedram:
Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime. 341-348
Poster Session and Mixer
- Amir Momeni, Perhaad Mistry, David R. Kaeli:
A parallel clustering algorithm for placement. 349-356 - Chessda Uttraphan, Nasir Shaikh-Husin, Mohamed Khalil Hani:
An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design. 357-364 - Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
Kriging bootstrapped neural network training for fast and accurate process variation analysis. 365-372 - Daniela De Venuto
Impedance modeling of the intracortical microelectrode for a reliable design of a brain activity recording system. 380-385 - Ying-Chi Li
Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representation. 386-391 - Yijie Huangfu, Wei Zhang:
Compiler-directed leakage energy reduction for instruction scratch-pad memories. 392-399 - Guilherme M. Castilhos, Eduardo Wächter
A framework for MPSoC generation and distributed applications evaluation. 408-411 - Varadan Savulimedu Veeravalli, Andreas Steininger
Architecture for monitoring SET propagation in 16-bit Sklansky adder. 412-419 - Rafael M. Madeira, Edna Barros
Towards more reliable embedded systems through a mechanism for monitoring driver devices communication. 420-427 - Takashi Sato
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. 428-433 - Eman El Mandouh:
Application of six-sigma DMAIC methodology in the evaluation of test effectiveness: A case study for EDA tools. 434-441 - Hoda Pahlevanzadeh, Qiaoyan Yu:
Systematic analyses for latching probability of single-event transients. 442-449
Session 4A: Reliability and Aging
- Mitsuhiko Igarashi
Assessment of reliability impact on GHz processors with moderate overdrive. 456-460 - Dinesh Ganta, Leyla Nazhandali:
Study of IC aging on ring oscillator physical unclonable functions. 461-466 - Dinesh Ganta, Leyla Nazhandali:
Circuit-level approach to improve the temperature reliability of Bi-stable PUFs. 467-472 - Halil Kukner, Moustafa A. Khatib
Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology. 473-479 - Vikram B. Suresh, Wayne P. Burleson:
Fine grained wearout sensing using metastability resolution time. 480-483 - Senthil Arasu, Mehrdad Nourani, Frank Cano, John M. Carulli, Vijay Reddy:
Asymmetric aging of clock networks in power efficient designs. 484-486
Session 4B: Advances in Timing Closure and Yield/Reliability Improvement
- Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark:
Methodology to optimize critical node separation in hardened flip-flops. 486-490 - Hyungjung Seo, Taewhan Kim:
Post-silicon tunable clock buffer allocation based on fast chip yield computation. 490-495 - Andrew B. Kahng, Hyein Lee:
Timing margin recovery with flexible flip-flop timing model. 496-503 - Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation. 504-509
Session 4C: New Ideas in Circuit Design
- Sandeep Koranne:
Constructing small-signal equivalent impedances using ellipsoidal norms. 510-516 - Mehrdad Khatir, Leyla Nazhandali:
Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit. 517-522 - Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii:
Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS. 523-528 - Sung S.-Y. Hsueh, Ryan H.-M. Huang, Charles H.-P. Wen
TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits. 529-534 - Santhosh Kumar Rethinagiri, Oscar Palomar
PETS: Power and energy estimation tool at system-level. 535-542 - Keunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi:
Impact of FinFET technology for power gating in nano-scale design. 543-547 - Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Avoiding unnecessary write operations in STT-MRAM for low power implementation. 548-553 - Chao Sun, Ayumi Soga, Takahiro Onagi, Koh Johguchi, Ken Takeuchi:
A workload-aware-design of 3D-NAND flash memory for enterprise SSDs. 554-561 - Md. Abir Khan, Saraju P. Mohanty, Elias Kougianos:
Statistical process variation analysis of a graphene FET based LC-VCO for WLAN applications. 569-574 - Tiansong Cui, Shuang Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram:
An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect. 575-581
Session 5B: Assertion and Formal Verification Technologies
- Hasan Sohofi, Zainalabedin Navabi:
Assertion-based verification for system-level designs. 582-588 - Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Coverage of compositional property sets under reactive constraints. 589-596 - Kai-Hui Chang, Yen-Ting Liu, Chris Browy:
Automated methods for eliminating X bugs. 597-603 - Amir Masoud Gharehbaghi
Specification and formal verification of power gating in processors. 604-610 - Miroslav N. Velev
Formal verification of safety of polymorphic heterogeneous multi-core architectures. 611-617 - Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le:
Simulation and satisfiability guided counter-example triage for RTL design debugging. 618-624
Session 5C: Thermal and Energy Considerations in Systems
- Darshan Gandhi, Andreas Gerstlauer, Lizy K. John:
FastSpot: Host-compiled thermal estimation for early design space exploration. 625-632 - Abhishek A. Sinkar, Hao Wang, Nam Sung Kim:
Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores. 633-638 - Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie:
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. 639-644 - Jacob Murray, Paul Wettin, Ryan Gary Kim
Thermal hotspot reduction in mm-Wave wireless NoC architectures. 645-652 - Florin Balasa, Noha Abuaesh, Cristian V. Gingu, Ilie I. Luican, Doru V. Nasui:
Energy-aware scratch-pad memory partitioning for embedded systems. 653-659 - Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan:
Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors. 660-666
Session 6A: Advanced Circuit and System Methodologies
- Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar:
ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes. 667-674 - Majid Jalalifar, Gyung-Su Byun:
An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs. 675-680 - Ting Chen, Xiaowei Pan, Hengzhu Liu, Tiebin Wu:
Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0. 681-687 - Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. 692-699 - Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
Statistical analysis of process variation induced SRAM electromigration degradation. 700-707 - Di-An Li, Malgorzata Marek-Sadowska:
Estimating true worst currents for power grid electromigration analysis. 708-714 - Le Zhang, Vivek Sarin:
An enlarged-partition based preconditioned iterative solver for parallel power grid simulation. 715-722 - Konstantis Daloukas, Nestor E. Evmorfopoulos, Panagiota E. Tsompanopoulou, George I. Stamoulis:
A 3-D Fast Transform-based preconditioner for large-scale power grid analysis on massively parallel architectures. 723-730 - Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu:
On pattern generation for maximizing IR drop. 731-737 - Yucai Wang, Vamsy P. Chodavarapu:
Design of a CMOS readout circuit for wide-temperature range capacitive MEMS sensors. 738-742 - Harald Steiner, Wilfried Hortschitz
Topology optimization of a passive thermal actuator. 743-747 - Thilo Sauter
Thermal flow sensors based on printed circuit board technology. 748-753 - Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh
Realization of efficient RF energy harvesting circuits employing different matching technique. 754-761 - Jiyuan Luan, Michael DiVita:
An integrated precision clock generator for implanted electronics with superior long-term stability. 762-765
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-26 20:31 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: