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ISPD 2011: Santa Barbara, California, USA
- Yao-Wen Chang, Jiang Hu:
Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011. ACM 2011, ISBN 978-1-4503-0550-1
Keynote address
- Massoud Pedram:
Robust design of power-efficient VLSI circuits. 1-2
Commemoration for Professor Ernest Kuh
- Ernest S. Kuh:
Professor Ernest Kuh's talk. 3-4 - Chung-Kuan Cheng:
Placement and beyond in honor of Ernest S. Kuh. 5-8 - Ren-Song Tsay:
From academic ideas to practical physical design tools. 9-12 - Malgorzata Marek-Sadowska:
On old and new routing problems. 13-20
Clock network synthesis and routing
- Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Grid-to-ports clock routing for high performance microprocessor designs. 21-28 - Tarun Mittal, Cheng-Kok Koh:
Cross link insertion for improving tolerance to variations in clock network synthesis. 29-36 - Shashank Bujimalla, Cheng-Kok Koh:
Synthesis of low power clock trees for handling power-supply variations. 37-44
Routing
- Yanheng Zhang, Chris Chu:
RegularRoute: an efficient detailed router with regular routing patterns. 45-52 - Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang:
An enhanced global router with consideration of general layer directives. 53-60 - Jin-Tai Yan
, Zhi-Wei Chen:
Obstacle-aware length-matching bus routing. 61-68 - Yang Zhao, Krishnendu Chakrabarty
Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips. 69-76
Physical design for 3D ICs
- Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
3DICs for tera-scale computing: a case study. 77-78 - Robert Patti:
Advances in 3D integrated circuits. 79-80 - Johann Knechtel, Igor L. Markov, Jens Lienig:
Assembling 2D blocks into 3D chips. 81-88
Placement and floorplanning
- Tung-Chieh Chen:
Automated placement for custom digital designs. 89-90 - Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. 91-98 - Xi Chen, Jiang Hu, Ning Xu:
Regularity-constrained floorplanning for multi-core processors. 99-106
Register clustering and placement
- Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak:
Power-driven flip-flop merging and relocation. 107-114 - Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang, Evan Y.-W. Tsai, Lancer S.-F. Chen:
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs. 115-122 - Dongjin Lee, Igor L. Markov:
Obstacle-aware clock-tree shaping during placement. 123-130 - Jianchao Lu, Xiaomi Mao, Baris Taskin:
Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. 131-138
DFM routing and routability-driven placement contest
- Alexander Volkov:
Impact of manufacturing on routing methodology at 32/22 nm. 139-140 - Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite. 141-146
Design for manufacturing
- Wojciech Maly:
Vertical slit transistor based integrated circuits (veSTICs): feasibility study. 147-148 - Vivek Singh:
Litho and design: moore close than ever. 149-150 - Kun Yuan, David Z. Pan:
E-beam lithography stencil planning and optimization with overlapped characters. 151-158
Circuit optimization and modeling
- Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang
More realistic power grid verification based on hierarchical current and power constraints. 159-166 - Yi-Le Huang, Jiang Hu, Weiping Shi:
Lagrangian relaxation for gate implementation selection. 167-174 - Fang Gong, Hao Yu, Lei He:
Stochastic analog circuit behavior modeling by point estimation method. 175-182
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