default search action
9. IDT 2014: Algeries, Algeria
- 9th International Design and Test Symposium, IDT 2014, Algeries, Algeria, December 16-18, 2014. IEEE 2014, ISBN 978-1-4799-8200-4
Keynotes
- Greg Hinckley:
Day 1 keynote: EDA's key to success: Riding waves of innovation. xii - Mohamed Djadoudi:
Day 1: Invited talk 1: IC qualification, testing & manufacturing using advanced package offerings & adequate process technologies. xiii - Hans G. Kerkhoff:
Day 1: Invited talk 2: Dependable mixed-signal integrated systems under aging. xiv - Mojy C. Chian:
Day 2 keynote: IoT fosters semiconductor innovation. xv - Paulo Freitas:
Day 2: Invited talk spintronic microsystems: Integrating analog devices with CMOS. xvi - Zebo Peng:
Day 2: Mini-tutorial: Challenges to the design and optimization of cyber-physical systems. xvii
Technical Papers
Session 1: Industrial Track
- Peter Sarson:
RF filter characterization using a chirp. 1-5 - Hakim Saheb, Syed Haider:
Scalable high speed serial interface for data converters: Using the JESD204B industry standard. 6-11 - Samir Boubezari, Jayant Chhabria:
Failure and root cause analysis for a system-on-chip: An industrial case study. 12 - Omar Kebichi:
Design, manufacturing & test of integrated circuits in the nanotechnology era. 13-17
Session 2: JTAG and Hardware/Software Co-design
- Ahmed Ibrahim
, Hans G. Kerkhoff:
iJTAG integration of complex digital embedded instruments. 18-23 - Abd-Elrahman G. Qoutb
High speed special function unit for graphics processing unit. 24-29 - Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kiamal Z. Pekmestzi, Costas Efstathiou:
High performance MAC designs. 30-35 - Magdy A. El-Moursy, Ayman Sheirah, Mona Safar, Ashraf Salem
Efficient embedded SoC hardware/software codesign using virtual platform. 36-38
Session 3: Test & Reliability
- Nikolaos Eftaxiopoulos-Sarris, Nicholas Axelos, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
An independent dual gate SOI FinFET soft-error resilient memory cell. 39-44 - Hakob Hakobyan, Paolo Rech, Matteo Sonza Reorda
Early reliability evaluation of a biomédical system. 45-50
Session 4: Mixed Signal Design & Test
- Ayssar Serhan, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Low-cost EVM built-in test of RF transceivers. 51-54 - Ahcène Bounceur, Belkacem Brahmi, Kamel Beznia, Reinhardt Euler:
Accurate analog/RF BIST evaluation based on SVM classification of the process parameters. 55-60
Session 5: Special Session on Nonvolatile memories
- Elena I. Vatajelu
Nonvolatile memories: Present and future challenges. 61-66 - S. Arcaro, Stefano Di Carlo
Integration of STT-MRAM model into CACTI simulator. 67-72
Session 6: Analog, RF & Digital Design
- Sherif M. Saif, Mohamed Dessouky, Salwa M. Nassar, Hazem M. Abbas
Exploiting satisfiability modulo theories for analog layout automation. 1-6 - Yasmina Belaroussi, Abdelhalim Slimane, Mohand-Tahar Belaroussi, Mohamed Trabelsi
RF and non-linearity characterization of porous silicon layer for RF-ICs. 79-82 - Mohannad Elshawy, Mohamed Dessouky, Sherif M. Saif, Sherif Mansour, Ed Petrus:
Multi-device layout templates for nanometer analog design. 83-88 - Shahab A. Najmi, Abdulfattah Mohammad Obeid, Mohammed S. BenSaleh:
WaferCatalyst - Towards promotion of IC design in the middle east using virtual community approach. 89-93 - Khaled Salah
A UVM-based smart functional verification platform: Concepts, pros, cons, and opportunities. 94-99
Session 7: Formal Verification, Reliability & Security
- Mehdi Dehbashi, Görschwin Fey
SAT-based speedpath debugging using X traces. 100-105 - Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß:
Automated formal verification of X propagation with respect to testability issues. 106-111 - Ghania Ait Abdelmalek, Rezki Ziani:
Impact analysis of resistive bridge within deep submicron Secured CMOS circuits. 112-117 - Cuiping Shao, Huiyun Li, Guoqing Xu, Xiaobo Hu:
Design for security test on cryptographic ICs for design-time security evaluation. 1-6
Session 8: Test Generation & Synthesis
- József Sziray:
Computational complexity in test-generation algorithms. 124-129 - Raimund Ubar
Modeling sequential circuits with shared structurally synthesized BDDs. 130-135 - Sayak Chakraborti, Paturi Varun Chowdhary, Kamalika Datta, Indranil Sengupta:
BDD based synthesis of Boolean functions using memristors. 136-141
Session 9: Reliability & Computation
- Amel Chenouf
Reliability analysis of CMOS inverter subjected to AC & DC NBTI stresses. 142-146 - Alvaro Velasquez, Sumit Kumar Jha
Parallel computing using memristive crossbar networks: Nullifying the processor-memory bottleneck. 147-152 - Yamna Bakha, Yassine Djeridane, Walid Aouimeur, Lamia Menasri, Abderrazak Smatti, Saad Hamzaoui:
ZnO based gas sensor testing. 1-3 - Kaouther Guesmi, Salem Hasnaoui:
Translating of MATLAB/SIMULINLK model to synchronous dataflow graph for parallelism analysis and programming embedded multicore systems. 156-161 - Sabrina Titri, Cherif Larbes
Rapid prototyping of PVS into FPGA: From model based design to FPGA/ASICs implementation. 162-167
Session 10: Arithmetic FPGA Implementation
- El-sedik Lamini, Rima Bellal, Samir Tagzout, Hacène Belbachir, Adel Belouchrani:
Enhanced bit-width optimization for linear circuits with feedbacks. 168-173 - Abdelkrim Kamel Oudjida, Ahmed Liacha
A new binary arithmetic for finite-word-length linear controllers: MEMS applications. 174-179 - Khaldoon Moosa Mhaidat, Abdulmughni Y. Hamzah:
A new efficient reduction scheme to implement tree multipliers on FPGAs. 180-184
Poster Sessions
Analog & RF Design
- Abdelkader Taibi, Abdelhalim Slimane, Sid-Ahmed Tedjini-Bailiche
A 0.9 V low power reconfigurable CMOS folded cascode LNA for multi-standard wireless applications. 185-188 - Abdelhalim A. Saadi, Mustapha C. E. Yagoub, Rachida Touhami:
A comparative study of various microstrip bandpass filters topologies for UWB applications. 189-192
Digital Design & Verification
- Ghada Moussa Bahig, Amr El-Kadi, Ashraf Salem
Formal verification of AUTOSAR FlexRay state manager. 193-198 - Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi:
A high radix montgomery multiplier with concurrent error detection. 199-204 - Kostas Tsoumanis, Constantinos Efstathiou, Kiamal Z. Pekmestzi:
Modulo 2n+1 addition and multiplication for redundant operands. 205-210 - Nejib Mediouni, Samir Ben Abid, Oussama Kallel, Kaouthar Guesmi, Salem Hasnaoui:
Design and implementation of Wishbone bridge for an iSLIP based NoC. 211-214 - Haichour Amina Selma, M'hamed Hamadouche:
A survey of GF (2m) multipliers on FPGA. 215-218 - Dichou Karima, Victor Tourtchine, Rahmoune Faycal:
An improved electronic voting machine using a microcontroller and a smart card. 219-224 - Nadjia Anane, Mohamed Anane:
High throughput parallel montgomery modular exponentiation on FPGA. 225-230
Test & Reliability
- Mohamed Boubaaya, Hakim Tahi, Boualem Djezzar
Reaction-diffusion model for interface traps induced by BTS stress including H+, H and H2 as diffusion species. 231-235 - Benkechkache Mohamed El Amine
Analytical approach of the impact of through silicon via on the performance of MOS devices. 242-247 - Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado:
Reliability assessment of backward error recovery for SRAM-based FPGAs. 248-252
IC/MEMS Solar Cell Modeling
- Khaled Salah
TSV-based 3D integration fabrication technologies: An overview. 253-256 - Lakhdari Abdelghani, MekkakiaMaaza Nasr-Eddine, Maamar Azouza, Bouguenna Abdellah, Kichene Moadh:
Modeling of silicon MEMS capacitive pressure sensor for biomédical applications. 263-266 - Hakim Tahi, Boualem Djezzar
Investigation of defect microstructures responsible for NBTI degradation using effective dipole moment extraction. 236-241
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-14 20:48 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: