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ICCD 1997: Austin, Texas, USA
- Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997. IEEE Computer Society 1997, ISBN 0-8186-8206-X
Session 1.1: Keynote Speech
- David A. Patterson, Krste Asanovic, Aaron B. Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos E. Kozyrakis, David R. Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, Katherine A. Yelick:
Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures. 2-7
Session 1.2: CAD Plenary
- Ronald A. Rohrer:
A Brief History of the Future of Semiconductor Electronic Design Automation. 10-11
Session 1.3.1: Special Session: Industrial Application of Formal Verification
- Gabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan:
Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor. 16-24 - Matt Kaufmann, Carl Pixley:
Intertwined Development and Formal Verification of a 60x Bus Model. 25-30 - Bishop Brock, Warren A. Hunt Jr.:
Formally Specifying and Mechanically Verifying Programs for the Motorola Complex Arithmetic Processor DSP. 31-36 - Jacob Savir:
BIST-Based Fault Diagnosis in the Presence of Embedded Memories. 37-47 - Yong Seok Kang, Jong Cheol Lee, Sungho Kang:
Built-in Self Test for Contect Addressable Memories. 48-53 - Nur A. Touba, Edward J. McCluskey:
Pseudo-Random Pattern Testing of Bridging Faults. 54-60
Session 1.3.3: Simulation and Power Estimation
- Serban Bruma, Ralph H. J. M. Otten:
Novel Simulation of Deep-Submicron MOSFET Circuits. 62-67 - Hoon Choi, Seung Ho Hwang:
Time-Stamped Transition Density for the Estimation of Delay Dependent Switching Activities. 68-73 - Benjamin Chen, Ivailo M. Nedelchev:
Power Compiler: A Gate-Level Power Optimization and Synthesis System. 74-79
Session 1.3.4: Branch Prediction
- Maria-Dana Tarlescu, Kevin B. Theobald, Guang R. Gao:
Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy. 82-87 - I-Cheng K. Chen, Chih-Chieh Lee, Matt Postiff, Trevor N. Mudge:
Design Optimization for High-speed Per-address Two-level Branch Predictors. 88-96 - Carl Burch:
PA-8000: A Case Study of Static and Dynamic Branch Prediction. 97-105
Session 1.4.1: New Techniques for Gate-Sizing and Retiming
- Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy:
Discrete Drive Selection for Continuous Sizing. 110-115 - Peichen Pan:
Continuous Retiming: Algorithms and Applications. 116-121 - Arvind K. Karandikar, Peichen Pan, C. L. Liu:
Optimal Clock Period Clustering for Sequential Circuits with Retiming. 122-127
Session 1.4.2: Circuit Modeling
- Rakesh Mehrotra, Massoud Pedram, Xunwei Wu:
Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells. 130-135 - Andreas C. Cangellaris, W. Pinello, Albert E. Ruehli:
Circuit-Based Description and Modeling of Electromagnetic Noise Effects in Packaged Low-Power Electronics. 136-142 - Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning:
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. 143-148
Session 1.4.3: Novel Architectures
- Xingbin Zhang, Ali Dasdan, Martin Schulz, Rajesh K. Gupta, Andrew A. Chien:
Architectural Adaptation for Application-Specific Locality Optimization. 150-156 - Minoru Inamori, Kenji Ishii, Akihiro Tsutsui, Kazuhiro Shirakawa, Hiroshi Nakada, Toshiaki Miyazaki:
A New Processor Architecture for Digital Signal Transport Systems. 157-162
Short Papers
- Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. 164-169 - Maurício Breternitz Jr.
, Roger Smith:
Enhanced Compression Techniques to Simplify Programm Decompression and Execution. 170-176
Session 1.4.4: Low Power Architectures
- R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
A Low Power Approach to Floating Point Adder Design. 178-185 - Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi:
Design and Implementation of Low-Power Digit-Serial Multipliers. 186-195 - Khurram Muhammad, Kaushik Roy:
On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution. 196-201
Session 1.5.1: Timing Optimization for Deep Submicron Technology
- Shervin Hojat, Paul Villarrubia:
An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors. 206-210 - Hirendu Vaishnav, Chi-Keung Lee, Massoud Pedram:
Post Layout Speed-up by Event Elimination. 211-216 - Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong
Clustering and Load Balancing for Buffered Clock Tree Synthesis. 217-223 - Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi:
CMOS Gate Delay Models for General RLC Loading. 224-229
Session 1.5.2: Special Session: The G4 S/390 Microprocessor
- Kenneth L. Shepard, Sean M. Carey, Daniel K. Beece, Robert F. Hatch, Gregory A. Northrop:
Design Methodology for the High-Performance G4 S/390. 232-240 - Charles F. Webb, John S. Liptay:
A High-Frequency Custom CMOS S/390 Microprocessor. 241-246 - James D. Warnock, Leon J. Sigal, Brian W. Curran, Yuen H. Chan:
High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. 247-252 - Arthur Tuminaro:
A 400MHz, 144Kb CMOS ROM Macro for an IBM S/390-Class Microprocessor. 253-255
Session 1.5.3: Multiprocessor Communication
- Robert Castañeda, Xiaodong Zhang, James M. Hoover Jr.:
A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex Exemplar. 258-266 - Hitoshi Oi, N. Ranganathan:
Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. 267-272 - Michael Kozuch, Wayne H. Wolf, Andrew Wolfe:
An Approach to Network Caching for Multimedia Objects. 273-278 - W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. 279-285
Session 1.5.4: Asynchronous Architectures
- Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya:
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. 288-294 - Andrew Davey, David Lloyd:
An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures. 295-300 - Fu-Chiung Cheng:
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits. 301-306 - David S. Bormann, Peter Y. K. Cheung:
Asnchronous Wrapper for Heterogeneous Systems. 307-314
Session 1.6.1: Panel: The War of the Roses: Designers versus Tool Developers
Session 1.6.2: Panel: If Software is King for Systems-on-Silicon, What's New in Compilers?
Session 2.1: Design and Test Plenary
- William H. Joyner Jr.:
Design and Test: The Lost World. 328
Session 2.2.1: Binary Decision Diagrams
- Somesh Jha, Yuan Lu, Marius Minea, Edmund M. Clarke:
Equivalence Checking Using Abstract BDDs. 332-337 - Christoph Meinel, Anna Slobodová:
Speeding up Variable Reordering of OBDDs. 338-343 - Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. 344-351 - Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton:
Timed Binary Decision Diagrams. 352-357
Session 2.2.2: Advanced Test Topics
- Irith Pomeranz, Sudhakar M. Reddy:
Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. 360-365 - Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis:
Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms. 366-371 - Ronald D. Blanton, John P. Hayes:
Properties of the Input Pattern Fault Model. 372-380 - Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. 381-386
Session 2.2.3: Embedded Software and Systems
- Yanbing Li, Miodrag Potkonjak, Wayne H. Wolf:
Real-Time Operating Systems for Embedded Computing. 388-392 - David L. Rhodes, Wayne H. Wolf:
Allocation and Data Arrival Design of Hard Real-time Systems. 393-399 - Alberto Allara, S. Filipponi, William Fornaciari
Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. 400-405
Session 2.2.4: Low Power Issues
- Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel:
Power Constrained Design of Multiprocessor Interconnection Networks. 408-416 - Peter Soderquist, Miriam Leeser:
Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. 417-422 - José A. Tierno, Prabhakar Kudva:
Asynchronous Transpose-Matrix Architectures. 423-428 - Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu:
A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. 429-434
Session 2.3.1: Formal Verification Methods
- Alan J. Hu, Masahiro Fujita, Chris Wilson:
Formal Verification of the HAL S1 System Cache Coherence Protocol. 438-444 - Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
A Survey of Techniques for Formal Verification of Combinational Circuits. 445-454 - William Canfield, E. Allen Emerson, Avijit Saha:
Checking Formal Specifications under Simulation. 455-460
Session 2.3.2: Mixed Signal Design and Test
- Karim Arabi, Bozena Kaminska:
Built-In Temperature Sensors for On-line Thermal Monitoring of Microelectronic Structures. 462-467 - Cheng-Ping Wang, Chin-Long Wey:
Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits. 468-473 - Jin Chen, Akhileswaran Ramachandran:
A Novel Test Set Design for Parametric Testing of Analog and Mixed-Signal Circuits. 474-480
Session 2.3.3: FPGA Design
- Fung Yu Young, D. F. Wong
On the Construction of Universal Series-Parallel Functions for Logic Module Design. 482-488 - Jörn Stohmann, Erich Barke:
A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. 489-495 - Wai-Kei Mak, D. F. Wong
Channel Segmentation Design for Symmentrical FPGAs. 496-501
Session 2.3.4: Cache Technology I
- Chenxi Zhang, Xiaodong Zhang, Yong Yan:
Multi-Column Implementations for Cache Associativity. 504-509 - Lizy Kurian John, Akila Subramanian:
Design and Performance Evaluation of a Cache Assist to implement Selective Caching. 510-518 - Jude A. Rivers, Edward S. Tam, Edward S. Davidson:
On Effective Data Supply For Multi-Issue Processors. 519-528
Session 2.4.1: Embedded Tutorial
- Kenneth L. Shepard:
Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits. 532-541
Session 2.4.2: Fault Diagnosis
- Wilfrido Alejandro Moreno, Fernando J. Falquez, John R. Samson Jr., Thomas Smith:
First Test Results of System Level Fault Tolerant Design Validation Through Laser Fault Injection. 544-548 - Craig Hunter:
Integrated Diagnostics for Embedded Memory Built-in Self Test on Power PCTM Devices. 549-554 - Cristiana Bolchini, Donatella Sciuto, Fabio Salice:
A TSC Evaluation Function for Combinational Circuits. 555-560
Session 2.4.3: Special Session: Low Power Design Issues
- Chih-Tung Chen, Kayhan Küçükçakar:
An Architectural Power Optimization Case Study using High-level Synthesis. 562-570 - Russell E. Henning, Chaitali Chakrabarti:
High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder. 571-576
Session 2.4.4: Cache Technology II
- Jih-Kwon Peir, Windsor W. Hsu:
Fast Cache Access with Full-Map Block Directory. 578-586 - Preeti Ranjan Panda, Hiroshi Nakamura
A Data Alignment Technique for Improving Cache Performance. 587-592 - I-Cheng K. Chen, Chih-Chieh Lee, Trevor N. Mudge:
Instruction Prefetching Using Branch Prediction Information. 593-601
Session 3.1: Architecture & Algorithm Plenary
- Randy H. Katz:
Is Wireless Data Dead? 604
Session 3.2.1: Layout Partitioning and Synthesis
- X. Tan, J. Tong, P. Tan, Nohpill Park, Fabrizio Lombardi:
An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits. 608-613 - Gregory Tumbush, Dinesh Bhatia:
Partitioning Under Timing and Area Constraints. 614-620 - John A. Chandy, Prithviraj Banerjee:
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement. 621-627 - Hai Zhou, D. F. Wong
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. 628-633
Session 3.2.2: Design for Testabiliy & Test Synthesis
- Kowen Lai, Christos A. Papachristou, Mikhail Baklashov:
High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains. 636-641 - Jing-Yang Jou, Ming-Chang Nien:
Power Driven Partial Scan. 642-647 - Ramesh C. Tekumalla, Premachandran R. Menon:
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. 648-653 - M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi
Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. 654-658
Session 3.2.3: Embedded Tutorial
- Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun:
Practical Advances in Asynchronous Design. 662-668
Session 3.2.4: Arithmetics
- Amit Mehrotra, Shaz Qadeer, Rajeev K. Ranjan, Randy H. Katz:
Benchmarking and Analysis of Architectures for CAD Applications. 670-675 - Keshab K. Parhi
Fast Low-Energy VLSI Binary Addition. 676-684 - Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano:
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. 685-689 - Yamin Li, Wanming Chu:
Parallel-Array Implementations of a Non-Restoring Square Root Algorithm. 690-695
Session 3.3.1: Asynchronous Design
- Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry:
Optimizing CMOS Implementations of the C-element. 700-705 - Rakefet Kol, Ran Ginosar:
A Double-Latched Asynchronous Pipeline. 706-712 - Wei Hwang, Rajiv V. Joshi, Walter H. Henkels:
A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. 712-717
Session 3.3.2: Special Session: Interconnect Modeling & Repeater Methodologies
- Norman Chang, Valery Kanevsky, O. Sam Nakagawa, Khalid Rahmat, Soo-Young Oh:
Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. 720-725 - David Li, Andrew Pua, Pranjal Srivastava, Uming Ko:
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. 726-731 - Zhang Zhu, Bradley S. Carlson:
Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family. 732-737
Session 3.3.3: Finite-State Machine and High-Level Synthesis
- Aurobindo Dasgupta, Shantanu Ganguly:
Divide & Conquer: A Strategy for Synthesis of Low Power Finite State Machines. 740-745 - Chuan-Yu Wang, Kaushik Roy:
Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. 746-751 - Sriram Govindarajan, Ranga Vemuri:
Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. 752-757
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