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ITC 2018: Phoenix, AZ, USA
- IEEE International Test Conference, ITC 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018. IEEE 2018, ISBN 978-1-5386-8382-8
- Meng Li, Kaveh Shamsi, Yier Jin
, David Z. Pan:
TimingSAT: Decamouflaging Timing-based Logic Obfuscation. 1-10 - Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. 1-10 - Andrew Stern, Ulbert Botero, Bicky Shakya, Hao-Ting Shen, Domenic Forte
EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs. 1-9 - I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram:
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis. 1-10 - Mengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty
Fault Tolerance for RRAM-Based Matrix Operations. 1-10 - Sourav Das, Fei Su, Sreejit Chakravarty:
A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing. 1-10 - Irith Pomeranz:
On Close-to-Functional Test Sequences. 1-8 - Christiana Kapatsori, Yu Liu, Angelos Antonopoulos, Yiorgos Makris
Hardware Dithering: A Run-Time Method for Trojan Neutralization in Wireless Cryptographic ICs. 1-7 - Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty
Self-Learning Health-Status Analysis for a Core Router System. 1-10 - Trevor Ault:
Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis. 1-6 - Matthew Nero, Chuanhe Jay Shan, Li-C. Wang, Nik Sumikawa:
Concept Recognition in Production Yield Data Analytics. 1-10 - Basim Shanyour, Spyros Tragoudas:
Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors. 1-10 - Fei Su, Prashant Goteti:
Improving Analog Functional Safety Using Data-Driven Anomaly Detection. 1-10 - Shuyue Lan, Chao Huang, Zhilu Wang, Hengyi Liang, Wenhao Su, Qi Zhu:
Design Automation for Intelligent Automotive Systems. 1-10 - Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian:
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. 1-10 - Tamzidul Hoque, Jonathan Cruz, Prabuddha Chakraborty
Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify. 1-10 - Erik Jan Marinissen
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. 1-10 - Yibo Lin, Mohamed Baker Alawieh
Machine Learning for Yield Learning and Optimization. 1-10 - Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn
XLBIST: X-Tolerant Logic BIST. 1-9 - Nicole Fern, Kwang-Ting (Tim) Cheng
Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security. 1-9 - M. Casarsa, Gurgen Harutyunyan:
Case Study and Advanced Functional Safety Solution for Automotive SoCs. 1-8 - Riccardo Cantoro
A New Technique to Generate Test Sequences for Reconfigurable Scan Networks. 1-9 - Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao
Electrical Modeling of STT-MRAM Defects. 1-10 - Teresa L. McLaurin, Ignatius P. Lawrence:
Improving Power, Performance and Area with Test: A Case Study. 1-10 - Shravan K. Chaganti
Fast and accurate linearity test for DACs with various architectures using segmented models. 1-10 - Ting-Yu Shen, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li, Samuel Pan:
Test methodology for PCHB/PCFB Asynchronous Circuits. 1-8 - Nathan Fulton, André Platzer
Safe AI for CPS (Invited Paper). 1-7 - Senwen Kan, Jennifer Dworak:
IJTAG Integrity Checking with Chained Hashing. 1-10 - Klas Leino, Shayak Sen, Anupam Datta, Matt Fredrikson
Influence-Directed Explanations for Deep Convolutional Networks. 1-8 - Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Nagib Hakim:
Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation. 1-10 - Tien-Phu Ho, Eric Faehn, Arnaud Virazel
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. 1-8 - Leonidas Katselas, Alkis A. Hatzopoulos
On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. 1-9 - Muhammad Yasin
Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition. 1-10 - Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutyunyan, N. Martirosyan, Yervant Zorian:
Advanced Uniformed Test Approach For Automotive SoCs. 1-10 - Arjun Chaudhuri, Krishnendu Chakrabarty
Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors. 1-10 - Michihiro Shintani
Artificial Neural Network Based Test Escape Screening Using Generative Model. 1-8 - Friedrich Hapke, Peter C. Maxwell:
Total Critical Area Based Testing. 1-10 - Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula:
Improving Diagnosis Resolution and Performance at High Compression Ratios. 1-8 - Hayk T. Grigoryan, Samvel K. Shoukourian, Gurgen Harutyunyan, Yervant Zorian, Costas Argyrides:
Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs. 1-6 - Kiyotaka Ichiyama, Takashi Kusaka, Masahiro Ishida:
A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces. 1-10 - Li-C. Wang:
An Autonomous System View To Apply Machine Learning. 1-10 - Ling Zhang, Zipeng Li, Krishnendu Chakrabarty
Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips. 1-10 - Ying Wang, Wen Li, Huawei Li, Xiaowei Li
Lightweight Timing Channel Protection for Shared DRAM Controller. 1-10 - Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty
Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism. 1-10 - Alif Ahmed, Farimah Farahmandi, Yousef Iskander, Prabhat Mishra
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution. 1-10 - Fakir Sharif Hossain, Michihiro Shintani
Variation-Aware Hardware Trojan Detection through Power Side-channel. 1-10 - Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Hypercompression of Test Patterns. 1-9 - Niveditha Manjunath, Dieter Haerle, Stephen Sabanal, Herbert Eichinger, Hermann Tauber, Andreas Machne, Christian Manthey, Mikko Vaananen, Radu Grosu, Dejan Nickovic:
Production Tests Coverage Analysis in the Simulation Environment. 1-7 - Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for In-System Automotive Test. 1-9 - Majid Ahadi Dolatsara, Huan Yu, Jose Ale Hejase, Wiren Dale Becker
Polynomial Chaos modeling for jitter estimation in high-speed links. 1-10 - Pallav Gupta:
An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug. 1-8 - Qicheng Huang, Chenlei Fang, Soumya Mittal
Improving Diagnosis Efficiency via Machine Learning. 1-10 - Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications. 1-10 - Mengyun Liu, Renjian Pan, Fangming Ye, Xin Li, Krishnendu Chakrabarty
Fine-Grained Adaptive Testing Based on Quality Prediction. 1-10 - Martin Andraud
On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs. 1-10 - Moritz Fieback
Testing Resistive Memories: Where are We and What is Missing? 1-9 - Mohammad Nasim Imtiaz Khan, Swaroop Ghosh:
Test of Supply Noise for Emerging Non-Volatile Memory. 1-10 - Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On New Class of Test Points and Their Applications. 1-9 - Will Howell, Friedrich Hapke, Edward Brazil, Srikanth Venkataraman, R. Datta, Andreas Glowatz, Wilfried Redemund, J. Schmerberg, Anja Fast, Janusz Rajski:
DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies. 1-10
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