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21st HPCA 2015: Burlingame, CA, USA
- 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 7-11, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-8930-0
- Nandhini Chandramoorthy, Giuseppe Tagliavini
, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini
Exploring architectural heterogeneity in intelligent vision systems. 1-12 - Arthur Perais
BeBoP: A cost effective predictor infrastructure for superscalar value prediction. 13-25 - Timothy Hayes
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors. 26-38 - Víctor Jiménez, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Francisco J. Cazorla
Increasing multicore system efficiency through intelligent bandwidth shifting. 39-50 - Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
Exploiting compressed block size as an indicator of future reuse. 51-63 - Nathan Beckmann, Daniel Sánchez:
Talus: A simple way to remove cliffs in cache performance. 64-75 - Xiaolong Xie, Yun Liang, Yu Wang
Coordinated static and dynamic cache bypassing for GPUs. 76-88 - Dong Li, Minsoo Rhu, Daniel R. Johnson, Mike O'Connor
Priority-based cache allocation in throughput processors. 89-100 - Jungrae Kim, Michael B. Sullivan, Mattan Erez
Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory. 101-112 - Xiaodong Wang, José F. Martínez
XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures. 113-125 - Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh:
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories. 126-136 - Yuhao Zhu, Matthew Halpern, Vijay Janapa Reddi:
Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applications. 137-149 - Nachiappan Chidambaram Nachiappan
Domain knowledge based energy management in handhelds. 150-160 - Jingwen Leng, Yazhou Zu, Vijay Janapa Reddi:
GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures. 161-173 - Ankit Sethia, Davoud Anoushe Jamshidi, Scott A. Mahlke:
Mascar: Speeding up GPU warps by reducing memory pitstops. 174-185 - Alberto Ros
Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies. 186-197 - Lucia G. Menezo, Valentin Puente
Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability. 198-209 - Misel-Myrto Papadopoulou, Xin Tong, André Seznec, Andreas Moshovos:
Prediction-based superpage-friendly TLB designs. 210-222 - Yu Du, Miao Zhou, Bruce R. Childers, Daniel Mossé, Rami G. Melhem:
Supporting superpages in non-contiguous physical memory. 223-234 - Mohammad A. Islam
Paying to save: Reducing cost of colocation data center via rewards. 235-245 - Vinicius Petrucci, Michael A. Laurenzano, John Doherty, Yunqi Zhang, Daniel Mossé, Jason Mars, Lingjia Tang:
Octopus-Man: QoS-driven task management for heterogeneous multicores in warehouse-scale computers. 246-258 - Ming Liu, Tao Li, Neo Jia, Andy Currid, Vladimir Troy:
Understanding the virtualization "Tax" of scale-out pass-through GPUs in GaaS clouds: An empirical study. 259-270 - Chang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, David Meisner, Thomas F. Wenisch, Jason Mars, Lingjia Tang, Ronald G. Dreslinski:
Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting. 271-282 - Amin Farmahini Farahani, Jung Ho Ahn
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules. 283-295 - Hao Wang, Chang-Jae Park, Gyungsu Byun, Jung Ho Ahn
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems. 296-308 - Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran
Reducing read latency of phase change memory via early read and Turbo Read. 309-319 - Rakan Maddah, Seyed Mohammad Seyedzadeh, Rami G. Melhem:
CAFO: Cost aware flip optimization for asymmetric memories. 320-330 - Devesh Tiwari, Saurabh Gupta, James H. Rogers, Don Maxwell, Paolo Rech
Understanding GPU errors on large-scale HPC systems and the implications for system design and operation. 331-342 - Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer:
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches. 343-353 - Neha Agarwal, David W. Nellans, Mike O'Connor
Unlocking bandwidth for GPUs in CC-NUMA systems. 354-365 - Manish Arora, Srilatha Manne, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems. 366-377 - Lizhong Chen, Di Zhu, Massoud Pedram, Timothy Mark Pinkston:
Power punch: Towards non-blocking power-gating of NoC routers. 378-389 - Ikki Fujiwara
Augmenting low-latency HPC network with free-space optical links. 390-401 - Nikolaos Chrysos, Cyriel Minkenberg, Mark Rudquist, Claude Basso, Brian Vanderpool:
SCOC: High-radix switches made of bufferless clos networks. 402-414 - Jongmin Won, Gwangsun Kim
Overcoming far-end congestion in large-scale networks. 415-427 - David J. Palframan, Nam Sung Kim, Mikko H. Lipasti:
iPatch: Intelligent fault patching to improve energy efficiency. 428-438 - Dong-Wan Kim, Mattan Erez
Balancing reliability, cost, and performance tradeoffs with FreeFault. 439-450 - Xinxin Jin, Soyeon Park, Tianwei Sheng, Rishan Chen, Zhiyong Shan, Yuanyuan Zhou:
FTXen: Making hypervisor resilient to hardware faults on relaxed cores. 451-462 - Henry Duwe, Xun Jian
Correction prediction: Reducing error correction latency for on-chip memories. 463-475 - Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu
Overcoming the challenges of crossbar resistive memory architectures. 476-488 - Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu:
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. 489-501 - Young Hoon Son, Sukhan Lee, Seongil O, Sanghyuk Kwon, Nam Sung Kim, Jung Ho Ahn
CiDRA: A cache-inspired DRAM resilience architecture. 502-513 - Sean Franey, Mikko H. Lipasti:
Tag tables. 514-525 - Kaisheng Ma
Architecture exploration for ambient energy harvesting nonvolatile processors. 526-537 - Nathan Beckmann, Po-An Tsai, Daniel Sánchez:
Scaling distributed cache hierarchies through computation and data co-scheduling. 538-550 - Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu:
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. 551-563 - Gene Y. Wu, Joseph L. Greathouse, Alexander Lyashevsky, Nuwan Jayasena, Derek Chiou:
GPGPU performance and power estimation using machine learning. 564-576 - Sam Likun Xi, Hans M. Jacobson, Pradip Bose, Gu-Yeon Wei, David M. Brooks:
Quantifying sources of error in McPAT and potential impacts on architectural studies. 577-589 - Minshu Zhao, Donald Yeung:
Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis. 590-602 - Thierry Moreau, Mark Wyse
SNNAP: Approximate computing on programmable SoCs via neural acceleration. 603-614 - Beayna Grigorian, Nazanin Farahpour, Glenn Reinman:
BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing. 615-626 - Sarah Neuwirth
Scalable communication architecture for network-attached accelerators. 627-638 - Casen Hunger, Mikhail Kazdagli, Ankit Singh Rawat
Understanding contention-based channels and using them for defense. 639-650 - Meltem Ozsoy, Caleb Donovick
Malware-aware processors: A framework for efficient online malware detection. 651-661 - Daniel Lo, Tao Chen, Mohamed Ismail, G. Edward Suh:
Run-time monitoring with adjustable overhead using dataflow-guided filtering. 662-674
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