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José-Ángel Gregorio
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- affiliation: Universidad de Cantabria
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2020 – today
- 2023
- [c39]Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio
, Valentin Puente:
Performance Characterization of Popular DNN Models on Out-of-Order CPUs. PACT 2023: 199-210 - 2022
- [c38]Alvaro Saiz, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio
Top-Down Performance Profiling on NVIDIA's GPUs. IPDPS 2022: 179-189 - 2021
- [j24]Pablo Prieto
Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking. IEEE Trans. Parallel Distributed Syst. 32(12): 2983-2995 (2021) - 2020
- [j23]Lucia G. Menezo
Rainbow: A composable coherence protocol for multi-chip servers. Concurr. Comput. Pract. Exp. 32(24) (2020) - [c37]Pablo Prieto
SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads. ICPP 2020: 54:1-54:11 - [i5]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
Rainbow: A Composable Coherence Protocol for Multi-Chip Servers. CoRR abs/2002.03944 (2020)
2010 – 2019
- 2019
- [j22]Valentin Puente, José-Ángel Gregorio
CLASSIC: A cortex-inspired hardware accelerator. J. Parallel Distributed Comput. 134: 140-152 (2019) - [c36]Adrian Colaso, Pablo Prieto
Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms. IPDPS 2019: 273-282 - [i4]Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio:
Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation. CoRR abs/1902.02837 (2019) - 2018
- [j21]Lucia G. Menezo
Mosaic: A Scalable Coherence Protocol. Int. J. Parallel Program. 46(6): 1110-1138 (2018) - [j20]Adrian Colaso, Pablo Prieto
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation. IEEE Trans. Parallel Distributed Syst. 29(5): 1161-1173 (2018) - 2017
- [j19]Lucia G. Menezo
An adaptive cache coherence protocol: Trading storage for traffic. J. Parallel Distributed Comput. 102: 163-174 (2017) - 2016
- [j18]Pablo Abad Fidalgo
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory. IEEE Trans. Parallel Distributed Syst. 27(1): 66-77 (2016) - [i3]Valentin Puente, José-Ángel Gregorio
CLAASIC: a Cortex-Inspired Hardware Accelerator. CoRR abs/1604.05897 (2016) - 2015
- [j17]Pablo Abad Fidalgo
Improving last level shared cache performance through mobile insertion policies (MIP). Parallel Comput. 49: 13-27 (2015) - [c35]Lucia G. Menezo, Valentin Puente
Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability. HPCA 2015: 198-209 - 2013
- [j16]Pablo Abad Fidalgo
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors. ACM Trans. Archit. Code Optim. 9(4): 37:1-37:21 (2013) - [c34]Lucia G. Menezo, Valentin Puente
The case for a scalable coherence protocol for complex on-chip cache hierarchies in many-core systems. PACT 2013: 279-288 - [c33]Pablo Abad Fidalgo
Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs. DSD 2013: 48-55 - [c32]Pablo Prieto
CMP off-chip bandwidth scheduling guided by instruction criticality. ICS 2013: 379-388 - 2012
- [j15]Pablo Abad Fidalgo
Balancing Performance and Cost in CMP Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 23(3): 452-459 (2012) - [j14]Pablo Abad Fidalgo
Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate. IEEE Trans. Parallel Distributed Syst. 23(11): 2010-2023 (2012) - [c31]Lucia G. Menezo, Valentin Puente
Improving coherence protocol reactiveness by trading bandwidth for latency. Conf. Computing Frontiers 2012: 143-152 - [c30]Pablo Abad Fidalgo
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip. ICCD 2012: 55-60 - [c29]Pablo Abad Fidalgo
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers. NOCS 2012: 99-106 - [i2]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
LOCKE Detailed Specification Tables. CoRR abs/1203.5349 (2012) - [i1]Javier Merino, Valentin Puente, José-Ángel Gregorio
The Necessity for Hardware QoS Support for Server Consolidation and Cloud Computing. CoRR abs/1206.6213 (2012) - 2011
- [j13]Pablo Prieto
Multilevel Cache Modeling for Chip-Multiprocessor Systems. IEEE Comput. Archit. Lett. 10(2): 49-52 (2011) - 2010
- [c28]Javier Merino, Valentin Puente, José-Ángel Gregorio
ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture. HPCA 2010: 1-10
2000 – 2009
- 2009
- [c27]Pablo Abad Fidalgo
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks. HPCA 2009: 355-366 - 2008
- [j12]José Miguel-Alonso
Improving the performance of large interconnection networks using congestion-control mechanisms. Perform. Evaluation 65(3-4): 203-211 (2008) - [j11]Javier Merino, Valentin Puente, Pablo Prieto
SP-NUCA: a cost effective dynamic non-uniform cache architecture. SIGARCH Comput. Archit. News 36(2): 64-71 (2008) - [j10]Valentin Puente
Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology. IEEE Trans. Computers 57(12): 1676-1689 (2008) - [c26]Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio:
Reducing the Interconnection Network Cost of Chip Multiprocessors. NOCS 2008: 183-192 - 2007
- [j9]Valentin Puente
Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks. IEEE Trans. Parallel Distributed Syst. 18(6): 776-788 (2007) - [c25]Pablo Abad Fidalgo
Rotary router: an efficient architecture for CMP interconnection networks. ISCA 2007: 116-125 - 2006
- [j8]Valentin Puente, José A. Gregorio
High-performance adaptive routing for networks with arbitrary topology. J. Syst. Archit. 52(6): 345-358 (2006) - [c24]José A. Gregorio
Topic 13: Routing and Communication in Interconnection Networks. Euro-Par 2006: 851 - [c23]Cruz Izu
Effects of Injection Pressure on Network Throughput. PDP 2006: 91-98 - 2005
- [c22]Cruz Izu
Evaluation of Interconnection Network Performance Under Heavy Non-uniform Loads. ICA3PP 2005: 396-405 - 2004
- [c21]Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio
A first glance at Kilo-instruction based multiprocessors. Conf. Computing Frontiers 2004: 212-221 - [c20]José Miguel-Alonso, José A. Gregorio
Load Unbalance in k-ary n-Cube Networks. Euro-Par 2004: 900-907 - [c19]Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide:
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism. ISCA 2004: 198-211 - [c18]Luis A. Amigo, Valentin Puente
Simulation Methodology for Decision Support Workloads. PDP 2004: 120-125 - [c17]Alejandro Gutiérrez, Rafael Menéndez de Llano, Francisco Cavero, José-Ángel Gregorio
Parallelization of a Neural Net Training Program in a Grid Environment. PDP 2004: 258-265 - [c16]Marco Galluzzi, Ramón Beivide, Valentin Puente
Evaluating kilo-instruction multiprocessors. WMPI 2004: 72-79 - 2003
- [j7]Valentin Puente
On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors. IEEE Trans. Parallel Distributed Syst. 14(5): 487-501 (2003) - [c15]Valentin Puente
A Low Cost Fault Tolerant Packet Routing for Parallel Computers. IPDPS 2003: 45 - [c14]Ramón Beivide, Carmen Martínez
Chordal Topologies for Interconnection Networks. ISHPC 2003: 385-392 - 2002
- [j6]José A. Gregorio
Modeling of interconnection subsystems for massively parallel computers. Perform. Evaluation 47(2/3): 105-129 (2002) - [c13]Valentin Puente, José A. Gregorio, Ramón Beivide:
SICOSYS: An Integrated Framework for studying Interconnection Network Performance in Multiprocessor Systems. PDP 2002: 15-22 - 2001
- [j5]Valentin Puente, Cruz Izu
The Adaptive Bubble Router. J. Parallel Distributed Comput. 61(9): 1180-1208 (2001) - [c12]Andres Ibañez, Valentin Puente, José A. Gregorio
A New Communication Mechanism for Cluster Computing. Euro-Par 2001: 793-800 - [c11]Valentin Puente, José A. Gregorio
A new routing mechanism for networks with irregular topology. SC 2001: 31 - 2000
- [c10]Valentin Puente, Cruz Izu, José A. Gregorio
Improving parallel system performance by changing the arrangement of the network links. ICS 2000: 44-53 - [c9]Carmen Carrión
Pipelining Router Design Improves Parallel System Performance. ISPAN 2000: 195-201 - [c8]Valentin Puente
A case study of trace-driven simulation for analyzing interconnection networks: cc-NUMAs with ILP processors. PDP 2000: 174-180
1990 – 1999
- 1999
- [c7]Valentin Puente, José A. Gregorio, Cruz Izu
Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications. Euro-Par 1999: 1222-1230 - [c6]Valentin Puente, Ramón Beivide, José A. Gregorio, J. M. Prellezo, José Duato
Adaptive Bubble Router: A Design to Improve Performance in Torus Networks. ICPP 1999: 58-67 - [c5]Valentin Puente, José A. Gregorio
Low-level router design and its impact on supercomputer system performance. International Conference on Supercomputing 1999: 193-201 - [c4]Carmen Carrión
Performance evaluation of the bubble algorithm: benefits for k-ary n-cubes. PDP 1999: 349-356 - 1998
- [c3]Carmen Carrión
Ghost packets: a deadlock-free solution for k-ary n-cube networks. PDP 1998: 133-139 - 1997
- [c2]Carmen Carrión
A flow control mechanism to avoid message deadlock in k-ary n-cube networks. HiPC 1997: 322-329 - 1996
- [j4]José Miguel-Alonso, Agustin Arruabarrena, Ramón Beivide, José-Ángel Gregorio
Assessing the Performance of the New IBM SP2 Communication Subsystem. IEEE Parallel Distributed Technol. Syst. Appl. 4(4): 12-22 (1996) - [j3]D. Conde, Rafael Menéndez de Llano, Michael González Harbour
A two-level programming strategy for distributed systems. Microprocess. Microprogramming 41(8-9): 541-554 (1996) - 1995
- [c1]José A. Gregorio
Petri Net Modeling of Interconnection Networks for Massively Parallel Architectures. International Conference on Supercomputing 1995: 107-116 - 1994
- [j2]Fernando Vallejo, José A. Gregorio
Shared Memory Multimicroprocessor Operating System with an Extended Petri Net Model. IEEE Trans. Parallel Distributed Syst. 5(7): 749-762 (1994) - 1992
- [j1]Mercedes Granda, José M. Drake, José A. Gregorio
Performance Evaluation of Parallel Systems by Using Unbounded Generalized Stochastic Petri Nets. IEEE Trans. Software Eng. 18(1): 55-71 (1992)
Coauthor Index
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last updated on 2024-10-07 21:16 CEST by the dblp team
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