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9th FPL 1999: Glasgow, UK
- Patrick Lysaght, James Irvine, Reiner W. Hartenstein:
Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings. Lecture Notes in Computer Science 1673, Springer 1999, ISBN 3-540-66457-2
Signal Processing
- Paul S. Graham, Brent E. Nelson:
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. 1-10 - M. Brucke, Arne Schulz, Wolfgang Nebel:
Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System. 11-20 - Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone:
SONIC - A Plug-In Architecture for Video Processing. 21-30
CAD Tools for DRL
- Kiran Bondalapati, Viktor K. Prasanna:
DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems. 31-40 - David Robinson, Patrick Lysaght:
Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework. 41-50
Optimization Studies
- Gregory C. Ahlquist, Brent E. Nelson, Michael Rice:
Optimal Finite Field Multipliers for FPGAs. 51-60 - Markus Weinhardt, Wayne Luk:
Memory Access Optimization and RAM Inference for Pipeline Vectorization. 61-70 - Silviu M. S. A. Chiricescu, Mankuan Michael Vai:
Analysis and Optimization of 3-D FPGA Design Parameters. 71-80
Physical Design
- John Marty Emmert, Dinesh Bhatia
:
Tabu Search: Ultra-Fast Placement for FPGAs. 81-90 - Juan de Vicente
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. 91-100 - Helena Krupnova, Gabriele Saucier:
Hierarchical Interactive Approach to Partition Large Designs into FPGAs. 101-110 - William K. C. Ho, Steven J. E. Wilton:
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. 111-123
Dynamically Reconfigurable Logic
- Milan Vasilko:
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems. 124-133 - E. Cantó, Juan Manuel Moreno, Joan Cabestany, Julio Faura, Josep Maria Insenser:
A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic. 134-143 - Gordon Charles McGregor, Patrick Lysaght:
Self Controlling Dynamic Reconfiguration: A Case Study. 144-154
Design Tools
- Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann:
An Internet Based Development Framework for Reconfigurable Computing. 155-164 - Andreas Koch:
On Tool Integration in High-Performance FPGA Design Flows. 165-174 - Karam S. Chatha, Ranga Vemuri
Hardware-Software Codesign for Dynamically Reconfigurable Architectures. 175-184
Reconfigurable Computing
- Wayne Luk, Arran Derbyshire, Shaori Guo, D. Siganos:
Serial Hardware Libraries for Reconfigurable Designs. 185-194 - Gordon J. Brebner, Neil W. Bergmann:
Reconfigurable Computing in Remote and Harsh Environments. 195-204 - Michael Eisenring, Marco Platzner, Lothar Thiele:
Communication Synthesis for Reconfigurable Embedded Systems. 205-214 - Steve Guccione, Delon Levi:
Run-Time Parameterizable Cores. 215-222
Applications
- Donald MacVicar, John W. Patterson, Satnam Singh:
Rendering Postscript Fonts on FPGAs. 223-232 - Stefan H.-M. Ludwig, Robert Slous, Satnam Singh:
Implementing Photoshop Filters in Virtex. 233-242 - Klaus Feske, Michael Scholz, Günther Döring, Denis Nareike:
Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler. 243-252 - Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung:
Quantitative Analysis of Run-Time Reconfigurable Database Search. 253-263
Novel Architectures
- Arnaud Tisserand, Pierre Marchal, Christian Piguet:
An On-Line Arithmetic Based FPGA for Low-Power Custom Computing. 264-273 - M. Imran Masud, Steven J. E. Wilton:
A New Switch Block for Segmented FPGAs. 274-281 - Gareth Jones:
PulseDSP - A Signal Processing Oriented Programmable Architecture. 282-290
Machine Applications
- Ilija Hadzic, Sanjay Udani, Jonathan M. Smith:
FPGA Viruses. 291-300 - Reetinder P. S. Sidhu, Alessandro Mei, Viktor K. Prasanna:
Genetic Programming Using Self-Reconfigurable FPGAs. 301-312 - Arnaldo S. R. Oliveira, Andreia Melo, Valery Sklyarov:
Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs. 313-322 - George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. 323-332
Short Papers
- Holger Kropp, Carsten Reuter, Matthias Wiege, Tien-Toan Do, Peter Pirsch:
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. 333-338 - Tomás Dulík:
An FPGA Implementation of Goertzel Algorithm. 339-346 - Mathew Wojko:
Pipelined Multipliers and FPGA Architectures. 347-352 - Emanuel M. Popovici, Patrick Fitzpatrick, Colin C. Murphy:
FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding. 353-358 - Juri Põldre, Kalle Tammemäe:
Reconfigurable Multiplier for Virtex FPGA Family. 359-364 - Iakovos Stamoulis, Martin White
Pipelined Floating Point Arithmetic Optimized for FPGA Architectures. 365-370 - Samuel Holmström:
SL - A Structural Hardware Design Language. 371-376 - R. Bruce Maunder, Zoran A. Salcic, George G. Coghill:
High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules. 377-384 - Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Mapping Applications onto Reconfigurable Kress Arrays. 385-390 - Martin Danek
Global Routing Models. 391-395 - Andrés D. García, Wayne P. Burleson, Jean-Luc Danger:
Power Modelling in Field Programmable Gate Arrays (FPGA). 396-404 - Dinesh Bhatia
NEBULA: A Partially and Dynamically Reconfigurable Architecture. 405-410 - Keith J. Symington, John F. Snowdon, Heiko Schroeder:
High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects. 411-416 - Torsten Kuberka, Andreas Kugel, Reinhard Männer, Holger Singpiel, Rainer Spurzem, Ralf Klessen:
AHA-GRAPE: Adaptive Hydrodynamic Architecture-GRAvity PipE. 417-424 - Malachy Devlin, Allan J. Cantle:
DIME - The First Module Standard for FPGA Based High Performance Computing. 425-430 - Michael Winston Dales:
The Proteus Processor - A Conventional CPU with Reconfigurable Functionality. 431-437 - Valeri F. Tomashau:
Logic Circuit Speeding up through Multiplexing. 438-443 - Philip James-Roxby, Elena Cerro-Prada
A Wildcarding Mechanism for Acceleration of Partial Configurations. 444-449 - Tsutomu Maruyama, Masaaki Takagi, Tsutomu Hoshino:
Hardware Implementation Techniques for Recursive Calls and Loops. 450-455 - Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation. 456-461 - María Dolores Valdés, María José Moure
An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis. 462-468 - Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx:
Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array's: An Integrated Approach Based on Reconfigurable Virtual Architectures. 469-474 - Sergej Sawitzki, Rainer G. Spallek:
A Concept for an Evaluation Framework for Reconfigurable Systems. 475-480 - Rainer Kress, Andreas Pyttel:
Debugging Application-Specific Programmable Products. 481-486 - Steve Casselman, John Schewel, Christophe Beaumont:
IP Validation for FPGAs Using Hardware Object Technology. 487-494 - Matthias Böge, Andreas Koch:
A Processor for Artificial Life Simulation. 495-500 - Craig Slorach, Steve Fulton, Ken Sharman:
A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGAs. 501-506 - Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker:
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. 507-513 - Tsutomu Maruyama, Tsutomu Hoshino:
A Reconfigurable Architecture for High Speed Computation by Pipeline Processing. 514-519 - Bernardo Kastrup
Seeking (the right) Problems for the Solutions of Reconfigurable Computing. 520-525 - Wong Hiu Yung, Wing Seung Yuen, Kin-Hong Lee, Philip Heng Wai Leong
A Runtime Reconfigurable Implementation of the GSAT Algorithm. 526-531 - Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz:
Accelerating Boolean Implications with FPGAs. 532-537
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