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FPGA 2024: Monterey, CA, USA
- Zhiru Zhang, Andrew Putnam:
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024. ACM 2024
Keynote I
- Timothy Sherwood
:
Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA. 1
Session: FPGA Circuit Design
- Alireza Khataei
CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond. 2-11 - Greg Stitt
Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet. 12-21 - Shaoxian Xu
MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs. 22-32 - Andy Ray
Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine. 33-39
Poster Session I
- Andrea Guerrieri
DynaRapid: From C to FPGA in a Few Seconds. 40 - Hui Wei
Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory. 40 - Andy Ray
Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design. 41 - Zelin Wang
XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud FPGAs. 41 - Muhammed Kawser Ahmed
ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA. 42 - Xiaoyu Niu
Accelerating Autonomous Path Planning on FPGAs with Sparsity-Aware HW/SW Co-Optimizations. 42 - Hassan Nassar
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels. 43 - Thore Gerlach
FPGA-Placement via Quantum Annealing. 43
Session: Applications I
- Ayatallah Elakhras
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. 44-54 - Jinming Zhuang
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. 55-66 - Zifan He
LevelST: Stream-based Accelerator for Sparse Triangular Solver. 67-77 - Sahand Kashani
A 475 MHz Manycore FPGA Accelerator for RTL Simulation. 78-84
Session: CAD for FPGAs
- Mahdi Abbaszadeh
From Topology to Realization in FPGA/VPR Routing. 85-96 - Louis-Noël Pouchet
Formal Verification of Source-to-Source Transformations for HLS. 97-107 - Dongjoon Park
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs. 108-118
Session: Datacenter and Cloud
- Zhenyu Xu
An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits. 119-129 - Will Lin
SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC. 130-141
Keynote II
- Prabhat K. Gupta
My Fifteen Year Journey of Deploying FPGA Accelerated Solutions. 142
Session: Applications II
- Chunyou Su
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. 143-153 - Manoj B. Rajashekar
HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs. 154-164 - Martin Langhammer
A Statically and Dynamically Scalable Soft GPGPU. 165-175 - Mark Klaisoongnoen
Evaluating Versal AI Engines for Option Price Discovery in Market Risk Analysis. 176-182
Poster Session II
- Yan Chen
A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAs. 183 - Geng Yang
E4SA: An Ultra-Efficient Systolic Array Architecture for 4-Bit Convolutional Neural Networks. 183 - Stéphane Pouget
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. 184 - Yiyue Jiang
Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. 184 - Kai Qian
AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator. 185 - Hongzheng Chen
A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. 185 - Shengjun Xu
HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN Model. 186 - Ruifan Xu
Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRs. 186 - Qizhe Wu
Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks. 187 - Zhigang Wei
Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning. 187
Session: High-Level Abstractions and Tools for FPGAs
- Jiahui Xu
Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. 188-198 - Xiaochen Hao
POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations. 199-210 - Youwei Xiao
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. 211-222
Session: Machine Learning
- Shulin Zeng
FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs. 223-234 - Daniel Gerlinghoff
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic. 235-245 - Yizhao Gao
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA. 246-257
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