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12. FPGA 2004: Monterey, CA, USA
- Russell Tessier, Herman Schmit:
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004. ACM 2004, ISBN 1-58113-829-6
Architectures
- Nicholas Weaver, John R. Hauser, John Wawrzynek:
The SFRA: a corner-turn FPGA architecture. 3-12 - Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck:
Exploration of pipelined FPGA interconnect structures. 13-22 - Arifur Rahman, Vijay Polavarapuv:
Evaluation of low-leakage design techniques for field programmable gate arrays. 23-30
Tools and architectures for power minimization
- Jason Helge Anderson, Farid N. Najm, Tim Tuan:
Active leakage power optimization for FPGAs. 33-41 - Fei Li, Yan Lin, Lei He, Jason Cong:
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. 42-50 - Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan:
Reducing leakage energy in FPGAs using region-constrained placement. 51-58
Applications I
- Paul Metzgen:
A high performance 32-bit ALU for programmable logic. 61-70 - Paul Kohlbrenner, Kris Gaj:
An embedded true random number generator for FPGAs. 71-78 - Sergio López-Buedo, Eduardo I. Boemo:
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. 79-86
Tools
- Tomasz S. Czajkowski, Jonathan Rose:
A synthesis oriented omniscient manual editor. 89-98 - Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou:
Incremental physical resynthesis for timing optimization. 99-108 - Deming Chen, Jason Cong, Fei Li, Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages. 109-117 - André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica
:
What is the right model for programming and using modern FPGAs? 119
Novel devices and approaches to programmable devices
- André DeHon, Michael J. Wilson:
Nanowire-based sublithographic programmable logic arrays. 123-132 - John Teifel, Rajit Manohar:
Highly pipelined asynchronous FPGAs. 133-142 - Steve Ferrera, Nicholas P. Carter:
A magnetoelectronic macrocell employing reconfigurable threshold logic. 143-151
Reconfigurable computing: analysis and trends
- Katherine Compton, Scott Hauck:
Flexibility measurement of domain-specific reconfigurable hardware. 155-161 - Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers:
A quantitative analysis of the speedup factors of FPGAs over processors. 162-170 - Keith D. Underwood:
FPGAs vs. CPUs: trends in peak floating-point performance. 171-180
Reconfigurable computing: architectures and applications
- Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
Application-specific instruction generation for configurable processor architectures. 183-189 - Lesley Shannon, Paul Chow:
Using reconfigurability to achieve real-time profiling for hardware/software codesign. 190-199 - Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter:
A reconfigurable unit for a clustered programmable-reconfigurable processor. 200-209
Applications II
- Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport:
An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. 213-222 - Zachary K. Baker, Viktor K. Prasanna:
Time and area efficient pattern matching on FPGAs. 223-232 - John F. Keane, Christopher Bradley, Carl Ebeling:
A compiled accelerator for biological cell signaling simulations. 233-241
Poster abstracts
- Anatole D. Ruslanov, Jeremy R. Johnson:
An FPGA implementation of bene permutation networks. 245 - Erik Chmelar:
Subframe multiplexing for FPGA manufacturing test configuration. 245 - Sherif M. Saif, Hazem M. Abbas
An FPGA implementation of block truncation coding for gray and color images. 245 - Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi:
Routing architecture for multi-context FPGAs. 246 - Richard Carbone, Andreas E. Savakis:
A flexible hardware architecture for 2-D discrete wavelet transform. 246 - Bret Woz, Andreas E. Savakis:
A VHDL MPEG-7 shape descriptor extractor. 246 - Daniel Denning, Malachy Devlin, James Irvine
Hardware co-simulation in system generator of the AES-128 encryption algorithm. 247 - Helmut Steckenbiller, Rudi Knorr:
Buffer schemes for runtime reconfiguration of function variants in communication systems. 247 - Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller:
Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. 247 - Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz:
High-speed systolic array for gene matching. 248 - Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald:
The gigahertz FPGA: design consideration and applications. 248 - Christopher C. Doss, Robert L. Riley Jr.:
FPGA-based implementation of single-precision exponential unit. 248 - Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee:
High level area, delay and power estimation for FPGAs. 249 - Jae-Jin Lee, Gi-Yong Song:
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. 249 - Ian Kuon, Aaron Egier, Jonathan Rose:
Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. 249 - Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi:
SPFD-based one-to-many rewiring. 250 - Joseph Zambreno, Rahul Simha, Alok N. Choudhary:
Addressing application integrity attacks using a reconfigurable architecture. 250 - Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris:
Fast adders in modern FPGAs. 250 - A. Manoj Kumar, B. Jayaram, V. Kamakoti:
SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. 251 - Mark L. Chang, Scott Hauck:
Least-significant bit optimization techniques for FPGAs. 251 - Martin Danek, Josef Kolár:
FPGA modelling for high-performance algorithms. 251 - Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. 252 - Michael J. Wirthlin:
Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement. 252 - Christophe Wolinski, Krzysztof Kuchcinski, Maya B. Gokhale:
A constraints programming approach to communication scheduling on SoPC architectures. 252 - Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow:
FPGA-based supercomputing: an implementation for molecular dynamics. 253 - Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. 253 - Paul Berube, José Nelson Amaral, Mike H. MacGregor:
An FPGA prototype for the experimental evaluation of a multizone network cache. 253 - Phan Cong Vinh, Jonathan P. Bowen
An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAs. 254 - Magesh Sadasivam, Sangjin Hong:
Dynamically reconfigurable architecture for high-throughput processing of data centric applications. 254 - Pronita Mehrotra, Mrugendra Singhai, Mike Pratt, Mark Cassada, Patrick Hamilton:
FPGA implementation of a high speed network interface card for optical burst switched networks. 255 - Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek:
Low energy FPGA interconnect design. 255 - Roland E. Wunderlich, James C. Hoe:
In-system FPGA prototyping of an itanium microarchitecture. 255 - Brian Leonard, Jeff Young, Ron Sass:
Online placement infrastructure to support run-time reconfiguration. 256 - Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee:
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. 256 - Ranjesh G. Jaganathan, Matthew Simpson, Ron Sass:
Automatic discovery, selection, and specialization of modules in RCADE. 256 - Vinay Verma, Shantanu Dutt:
Roving testing using new built-in-self-tester designs for FPGAs. 257 - Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. 257 - Bo Yang, Ramesh Karri
Divide and concatenate: a scalable hardware architecture for universal MAC. 258 - Thilo Pionteck
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. 258 - Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi:
Implementation of elliptic curve cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer. 259 - Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima, Paulo Romero Martins Maciel:
A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures. 259 - Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls:
Power analysis and estimation tool integrated with XPOWER. 259
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