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CODES+ISSS 2009: Grenoble, France
- Wolfgang Rosenstiel, Kazutoshi Wakabayashi:
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009. ACM 2009, ISBN 978-1-60558-628-1
Framworks for platform modeling and exploration
- Anders Sejer Tranberg-Hansen, Jan Madsen
:
A compositional modelling framework for exploring MPSoC systems. 1-10 - Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A high-level virtual platform for early MPSoC software development. 11-20 - Scott Sirowy, Bailey Miller, Frank Vahid:
Portable SystemC-on-a-chip. 21-30
Tools for embedded software design
- Sjoerd Meijer, Hristo Nikolov, Todor P. Stefanov
On compile-time evaluation of process partitioning transformations for Kahn process networks. 31-40 - Praveen Raghavan, Francky Catthoor:
SARA: StreAm register allocation. 41-50 - Ya-Shuai Lü, Li Shen, Zhiying Wang, Nong Xiao:
Dynamically utilizing computation accelerators for extensible processors in a software approach. 51-60
System level modeling and simulation
- Weichen Liu
An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking. 61-70 - Marius Gligor, Nicolas Fournel, Frédéric Pétrot:
Using binary translation in event driven simulation for fast and flexible MPSoC simulation. 71-80 - Christian Schröder, Wolfgang Klingauf, Robert Günzel, Mark Burton, Eric Roesler:
Configuration and control of SystemC models using TLM middleware. 81-88 - Heekyung Kim, Dukyoung Yun, Soonhoi Ha:
Scalable and retargetable simulation techniquesfor multiprocessor systems. 89-98
Architecture and routing for NoC
- Andreas Hansson, Kees Goossens:
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. 99-108 - Leonel Tedesco
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures. 109-118 - Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip. 119-128 - Shirish Bahirat, Sudeep Pasricha:
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. 129-136
Application specific alogorithms and architectures
- Xin He, Jorgen Peddersen, Sri Parameswaran
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. 137-146 - Jonathan Rohrer, Kubilay Atasu
Memory-efficient distribution of regular expressions for fast deep packet inspection. 147-154 - David Szczesny, Sebastian Hessel, Felix Bruns, Attila Bilgic:
On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices. 155-162
Embedded software systems
- Yangsup Lee, Sanghyuk Jung, Yong Ho Song:
FRA: a flash-aware redundancy array of flash storage devices. 163-172 - Andrea Acquaviva, Nicola Bombieri
Automatic customization of device drivers for IP-cores used with assorted CPU organizations. 173-182 - Arslan Munir
An MDP-based application oriented optimal policy for wireless sensor networks. 183-192
Power-aware design methodology
- Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles:
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems. 193-202 - Mohammad Ali Ghodrat, Tony Givargis:
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation. 203-210 - Chuan-Yue Yang, Jian-Jia Chen
Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processor. 211-220
Synthesis and analysis for variation and reliability
- Jason Cong, Albert Liu, Bin Liu:
A variation-tolerant scheduler for better than worst-case behavioral synthesis. 221-228 - Martin Lukasiewycz, Michael Glaß
Exploiting data-redundancy in reliability-aware networked embedded system design. 229-238 - Björn Sander, Jürgen Schnerr, Oliver Bringmann:
ESL power analysis of embedded processors for temperature and reliability estimations. 239-248
Embedded system optimization across memory hierarchy
- Chengmo Yang, Mingjing Chen, Alex Orailoglu:
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses. 249-256 - Rodrígo González-Alberquilla, Fernando Castro
Stack oriented data cache filtering. 257-266 - Meikang Qiu, Lei Zhang, Edwin Hsing-Mean Sha:
ILP optimal scheduling for multi-module memory. 277-286
Efficient techniques for architecture simulation
- Yi-Len Lo, Mao Lin Li, Ren-Song Tsay:
Cycle count accurate memory modeling in system level design. 287-294 - Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. 295-304 - Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
TotalProf: a fast and accurate retargetable source code profiler. 305-314 - Daniel Christopher Powell, Björn Franke
Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators. 315-324
System level reconfiguration and architecture optimization
- Vincenzo Rana
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. 325-334 - Lars Bauer, Muhammad Shafique
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. 335-342 - Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik
Supporting RTL flow compatibility in a microarchitecture-level design framework. 343-352
Emerging technique
- Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula:
A scalable parallel H.264 decoder on the cell broadband engine architecture. 353-362 - Martin Lukasiewycz, Michael Glaß
FlexRay schedule optimization of the static segment. 363-372 - Yongsoo Joo
Improving application launch times with hybrid disks. 373-382
Exploring the hardware software boundaries for MPSoC design
- Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal:
A tuneable software cache coherence protocol for heterogeneous MPSoCs. 383-392 - Jason Agron, David Andrews
Building heterogeneous reconfigurable systems with a hardware microkernel. 393-402 - Patrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot:
Native MPSoC co-simulation environment for software performance estimation. 403-412
Perfomance analysis and optimization for heterogeneous multiprocesses system
- Deepak Gangadharan
Fast model-based test case classification for performance analysis of multimedia MPSoC platforms. 413-422 - Alexander Viehl, Michael Pressler, Oliver Bringmann:
Bottom-up performance analysis considering time slice based software scheduling at system level. 423-432 - Simon Schliecker, Rolf Ernst:
A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems. 433-442 - Antonino Tumeo
Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach. 443-452
Architecture and optimization of NoC
- Yue Qian, Zhonghai Lu, Wenhua Dou:
Applying network calculus for performance analysis of self-similar traffic in on-chip networks. 453-460 - Paul Bogdan
Statistical physics approaches for network-on-chip traffic characterization. 461-470 - Glenn Leary, Karam S. Chatha:
Automated technique for design of NoC with minimal communication latency. 471-480 - Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø:
Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. 481-490
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