research-article

SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems

Authors:

Mohammad Shihabul Haque,

Andhi Janapsatya,

Sri ParameswaranAuthors Info & Claims

CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Pages 295 - 304

https://doi.org/10.1145/1629435.1629476

Published: 11 October 2009 Publication History

Abstract

Simulation of an application is a popular and reliable approach to find the optimal configuration of level one cache memory for an application specific embedded system processor. However, long simulation time is one of the main disadvantages of simulation based approaches. In this paper, we propose a new and fast simulation method, Super Set Simulator (SuSeSim). While previous methods use Top-Down searching strategy, SuSeSim utilizes a Bottom-Up search strategy along with a new elaborate data structure to reduce the search space to determine a cache hit or miss. SuSeSim can simulate hundreds of cache configurations simultaneously by reading an application's memory request trace just once. Total number of cache hits and misses are accurately recorded. Depending on different cache block sizes and benchmark applications, SuSeSim can reduce the number of tags to be checked by up to 43% compared to the existing fastest simulation approach (the CRCB algorithm). With the help of a faster search and an easy to maintain data structure, SuSeSim can be up to 94% faster in simulating memory requests compared to the CRCB algorithm.

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Cited By

Brais HKalayappan RPanda P(2020)A Survey of Cache SimulatorsACM Computing Surveys10.1145/337239353:1(1-32)Online publication date: 6-Feb-2020
https://dl.acm.org/doi/10.1145/3372393
Haque MEaswaran A(2018)Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time MulticoresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285708137:11(2720-2731)Online publication date: Nov-2018
https://doi.org/10.1109/TCAD.2018.2857081
Haque MVasudevan SNihar AEaswaran AKumar ATay Y(2018)A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2018.00024(116-123)Online publication date: May-2018
https://doi.org/10.1109/ISORC.2018.00024
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Index Terms

SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Hardware
  1. Hardware validation

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Published In

cover image ACM Conferences

CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

October 2009

498 pages

ISBN:9781605586281

DOI:10.1145/1629435

Program Chairs:
Wolfgang Rosenstiel
University of Tübingen, Germany
,
Kazutoshi Wakabayashi
NEC, Japan

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 October 2009

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ESWeek '09

Sponsor:

ESWeek '09: Fifth Embedded Systems Week

October 11 - 16, 2009

Grenoble, France

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Brais HKalayappan RPanda P(2020)A Survey of Cache SimulatorsACM Computing Surveys10.1145/337239353:1(1-32)Online publication date: 6-Feb-2020
https://dl.acm.org/doi/10.1145/3372393
Haque MEaswaran A(2018)Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time MulticoresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285708137:11(2720-2731)Online publication date: Nov-2018
https://doi.org/10.1109/TCAD.2018.2857081
Haque MVasudevan SNihar AEaswaran AKumar ATay Y(2018)A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2018.00024(116-123)Online publication date: May-2018
https://doi.org/10.1109/ISORC.2018.00024
Eusse JFernandez FLeupers RAscheid G(2016)Concurrent memory subsystem and application optimization for ASIP design2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818325(1-10)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818325
Nawinne IJavaid HRagel RRadhakrishnan SParameswaran S(2015)Exploring Multilevel Cache Hierarchies in Application Specific MPSoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244573634:12(1991-2003)Online publication date: Dec-2015
https://doi.org/10.1109/TCAD.2015.2445736
Schneider JPeddersen JParameswaran S(2015)Speeding up single pass simulation of PLRUt cachesThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059091(695-700)Online publication date: Jan-2015
https://doi.org/10.1109/ASPDAC.2015.7059091
Nawinne ISchneider JJavaid HParameswaran SFettweis GNebel W(2014)Hardware-based fast exploration of cache hierarchies in application specific MPSoCsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617020(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617020
Schneider JPeddersen JParameswaran S(2014)MASH{fifo}Proceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593159(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593159
Deng JLiang YLuo GSun G(2014)Rapid design space exploration of two-level unified caches2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865540(1937-1940)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865540
Schneider JPeddersen JParameswaran S(2014)A scorchingly fast FPGA-based Precise L1 LRU cache simulator2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742926(412-417)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742926
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