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CODES+ISSS 2007: Salzburg, Austria
- Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt
, Jürgen Teich:
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007, ISBN 978-1-59593-824-4
Tutorials
- Rodric M. Rabbah:
Beyond gaming: programming the PLAYSTATION®3 cell architecture for cost-effective parallel processing. 1 - Walid A. Najjar
Compiling code accelerators for FPGAs. 2
System-level design methods for MPSoC
- Brett H. Meyer, Donald E. Thomas:
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. 3-8 - Mark Thompson, Hristo Nikolov, Todor P. Stefanov
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. 9-14 - Chengmo Yang, Alex Orailoglu:
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules. 15-20
Specification language and model transformations to support synthesis and design
- Tarvo Raudvere, Ingo Sander
Synchronization after design refinements with sensitive delay elements. 21-26 - Wolfgang Klingauf, Robert Günzel, Christian Schröder:
Embedded software development on top of transaction-level models. 27-32 - Pramod Chandraiah, Rainer Dömer:
Pointer re-coding for creating definitive MPSoC models. 33-38
Embedded systems
- Hiroaki Inoue, Akihisa Ikeno, Tsuyoshi Abe, Junji Sakai, Masato Edahiro:
Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems. 39-44 - Pengyuan Yu, Patrick Schaumont
Secure FPGA circuits using controlled placement and routing. 45-50 - Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
A smart random code injection to mask power analysis based side channel attacks. 51-56 - Krutartha Patel, Sridevan Parameswaran
Ensuring secure program execution in multiprocessor embedded systems: a case study. 57-62
Heterogeneous computing platform simulation and debug
- Simon Künzli, Arne Hamann, Rolf Ernst, Lothar Thiele:
Combined approach to system level performance analysis of embedded systems. 63-68 - Alex Bobrek, JoAnn M. Paul, Donald E. Thomas:
Event-based re-training of statistical contention models for heterogeneous multiprocessors. 69-74 - Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
HySim: a fast simulation framework for embedded software development. 75-80 - Bruno C. Albertini
A computational reflection mechanism to support platform debugging in SystemC. 81-86
Static and dynamic techniques for partitioning and scheduling
- Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu
Energy efficient co-scheduling in dynamically reconfigurable systems. 87-92 - Greg Stitt, Frank Vahid:
Thread warping: a framework for dynamic synthesis of thread accelerators. 93-98 - Sascha Gädtke, Claus Traulsen, Reinhard von Hanxleden:
HW/SW co-design for Esterel processing. 99-104
Low power design and thermal control
- Seunghoon Kim, Robert P. Dick, Russ Joseph:
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems. 105-110 - Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Giovanni De Micheli:
Temperature-aware processor frequency assignment for MPSoCs using convex optimization. 111-116 - Chong Sun, Li Shang, Robert P. Dick:
Three-dimensional multiprocessor system-on-chip thermal optimization. 117-122 - Hermann Eul:
Complexity challenges towards 4th generation communication solutions. 123
Special session I
- Radu Marculescu
Fresh air: the emerging landscape of design for networked embedded systems. 124
Embedded software
- Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor:
Locality optimization in wireless applications. 125-130 - Hanno Scharwächter, Jonghee M. Youn
A code-generator generator for multi-output instructions. 131-136 - Paul Lokuciejewski, Heiko Falk, Martin Schwarzer, Peter Marwedel, Henrik Theiling:
Influence of procedure cloning on WCET prediction. 137-142 - Heiko Falk, Sascha Plazar, Henrik Theiling:
Compile-time decided instruction cache locking using worst-case execution paths. 143-148
Advances in NoC optimization
- Andreas Hansson, Martijn Coenen, Kees Goossens:
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. 149-154 - Glenn Leary, Krishna Mehta, Karam S. Chatha:
Performance and resource optimization of NoC router architecture for master and slave IP cores. 155-160 - Chen-Ling Chou, Radu Marculescu
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels. 161-166 - Leandro Fiorin, Gianluca Palermo
A data protection unit for NoC-based architectures. 167-172
System-level performance analysis
- Wolfgang Haid, Lothar Thiele:
Complex task activation schemes in system level performance analysis. 173-178 - Razvan Racu, Li Li, Rafik Henia, Arne Hamann, Rolf Ernst:
Improved response time analysis of tasks scheduled under preemptive Round-Robin. 179-184 - Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel:
Probabilistic performance risk analysis at system-level. 185-190
Case studies and emerging techniques
- A. C. H. Ng, Jan-Willem Weijers, Miguel Glassee, Thomas Schuster, Bruno Bougard, Liesbet Van der Perre
ESL design and HW/SW co-verification of high-end software defined radio platforms. 191-196 - Michael A. Baker, Aviral Shrivastava
Smart driver for power reduction in next generation bistable electrophoretic display technology. 197-202 - Siddharth Garg, Diana Marculescu
On the impact of manufacturing process variations on the lifetime of sensor networks. 203-208
Practical approaches to system-level performance analysis
- Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann
Performance modeling for early analysis of multi-core systems. 209-214 - Antoine Perrin, Frank Ghenassia:
Bridging gap between simulation and spreadsheet study. 215-216 - Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luca Benini
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions. 217-226
System-level synthesis
- Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. 227-232 - Paul Pop
Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems. 233-238 - Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, Li Shang:
Reliable multiprocessor system-on-chip synthesis. 239-244
Embedded systems architecture
- Chenjie Yu, Peter Petrov:
Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors. 245-250 - Benny Akesson
Predator: a predictable SDRAM memory controller. 251-256 - Siddharth Choudhuri, Tony Givargis:
Performance improvement of block based NAND flash translation layer. 257-262
Panel
- Rolf Ernst, Gernot Spiegelberg, Thomas Weber, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli
Automotive networks: are new busses and gateways the answer or just another challenge? 263
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