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CASES 2014: Uttar Pradesh, India
- Karam S. Chatha, Rolf Ernst, Anand Raghunathan, Ravishankar R. Iyer:
2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014. ACM 2014, ISBN 978-1-4503-3050-3 - Bilel Belhadj, Alexandre Valentian, Pascal Vivet
, Marc Duranton, Liqiang He, Olivier Temam:
The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators. 1:1-1:9 - Timo Viitanen
Heuristics for greedy transport triggered architecture interconnect exploration. 2:1-2:7 - Ryan Gary Kim
Energy-efficient VFI-partitioned multicore design using wireless NoC architectures. 3:1-3:9 - Narasinga Rao Miniskar
Retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applications. 4:1-4:9 - Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems. 5:1-5:10 - Martin Haaß, Lars Bauer, Jörg Henkel:
Automatic custom instruction identification in memory streaming algorithms. 6:1-6:9 - Rupesh Nasre
Auto-parallelization of data structure operations for GPUs. 7:1-7:10 - Mickaël Dardaillon
A compilation flow for parametric dataflow: Programming model, scheduling, and application to heterogeneous MPSoC. 8:1-8:10 - Kiran Chandramohan, Michael F. P. O'Boyle:
A compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCs. 9:1-9:10 - Isabella Stilkerich, Philip Taffner, Christoph Erhardt, Christian Dietrich, Christian Wawersich, Michael Stilkerich:
Team up: Cooperative memory management in embedded systems. 10:1-10:10 - Jing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen
A low-cost memory interface for high-throughput accelerators. 11:1-11:10 - Pooja Roy, Manmohan Manoharan, Weng-Fai Wong
EnVM: Virtual memory design for new memory architectures. 12:1-12:10 - Wei Quan, Andy D. Pimentel
A system-level simulation framework for evaluating task migration in MPSoCs. 13:1-13:9 - Sebastian Ottlik, Stefan Stattelmann, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann:
Context-sensitive timing simulation of binary embedded software. 14:1-14:10 - Harry Wagstaff, Tom Spink
Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators. 15:1-15:10 - Kai Hu, Trung Anh Dinh, Tsung-Yi Ho
Control-layer optimization for flow-based mVLSI microfluidic biochips. 16:1-16:10 - Stefan Hepp, Florian Brandner
Splitting functions into single-entry regions. 17:1-17:10 - Bryce Holton, Ke Bai, Aviral Shrivastava
Construction of GCCFG for inter-procedural optimizations in Software Managed Manycore (SMM) architectures. 18:1-18:10 - Matthew Schuchhardt, Susmit Jha, Raid Ayoub, Michael Kishinevsky, Gokhan Memik:
CAPED: Context-aware personalized display brightness for mobile devices. 19:1-19:10 - James Pallister, Kerstin Eder, Simon J. Hollis, Jeremy Bennett:
A high-level model of embedded flash energy consumption. 20:1-20:9 - Hao Wen, Wei Zhang:
Reducing cache leakage energy for hybrid SPM-cache architectures. 21:1-21:9 - Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele:
AdaPNet: Adapting process networks in response to resource variations. 22:1-22:10 - Qining Lu, Karthik Pattabiraman, Meeta Sharma Gupta, Jude A. Rivers:
SDCTune: A model for predicting the SDC proneness of an application for configurable protection. 23:1-23:10 - Weidong Shi, Yuanfeng Wen, Ziyi Liu, Xi Zhao, Dainis Boumber
Fault resilient physical neural networks on a single chip. 24:1-24:10
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