default search action
6th AICAS 2024: Abu Dhabi, United Arab Emirates
- 6th IEEE International Conference on AI Circuits and Systems, AICAS 2024, Abu Dhabi, United Arab Emirates, April 22-25, 2024. IEEE 2024, ISBN 979-8-3503-8363-8
- Junfeng Tan, Guosheng Yu, Jianing Li, Xiaohan Ma, Fang Bao, Evens Pan, David Bian, Yongfu Li, Yuan Du, Li Du, Bo Li, Wei Mao:
AICAS Grand Challenge 2024: Software and Hardware Co-optimization for General Large Language Model Inference on CPU. 1-5 - Sebastián Marzetti, Valentin Gies, Valentin Barchasz, Hervé Barthélemy, Hervé Glotin:
Analog Features Extractor for Ultra-Low Power Embedded AI Listening and Keyword Spotting. 1-5 - Cristian Cioflan, Lukas Cavigelli, Manuele Rusci, Miguel de Prado, Luca Benini:
On-Device Domain Learning for Keyword Spotting on Low-Power Extreme Edge Embedded Systems. 6-10 - Li Zhang, Ahmed M. Eltawil
, Khaled N. Salama
Hardware-Friendly Lightweight Convolutional Neural Network Derivation at The Edge. 11-15 - Yi-Ting Wu, Tzu-Yun Yen, Yu-Pei Lin, Bo-Cheng Lai:
HeteroEML: Heterogeneous Design Methodology of Edge Machine Learning on CPU+FPGA Platform. 16-20 - Dayoung Chun, Hyuk-Jae Lee, Hyun Kim:
PF-Training: Parameter Freezing for Efficient On-Device Training of CNN-based Object Detectors in Low-Resource Environments. 21-25 - Daniel Windhager, Bernhard Alois Moser, Michael Lunglmayr:
SNN Architecture for Differential Time Encoding Using Decoupled Processing Time. 26-30 - Zihang Song, Prabodh Katti, Osvaldo Simeone, Bipin Rajendran:
Stochastic Spiking Attention: Accelerating Attention with Stochastic Computing in Spiking Networks. 31-35 - Amélie Gruel, Adrien F. Vincent, Jean Martinet, Sylvain Saïghi:
Neuromorphic Event-based Line Detection on SpiNNaker. 36-40 - Lorenzo Pes, Rick Luiken, Federico Corradi, Charlotte Frenkel:
Active Dendrites Enable Efficient Continual Learning in Time-To-First-Spike Neural Networks. 41-45 - Hugo Bulzomi, Yuta Nakano, Rémy Bendahan, Jean Martinet:
Neuromorphic Temporal Pattern Detection with Spiking Neural Networks using Synaptic Delays. 46-50 - Syed Asrar ul Haq, Bhavesh Prasad Dangwal, Sumit Darak:
RNN-Based Low Complexity High Speed Channel Estimation Architectures for Vehicular Networks. 51-55 - Anurag Gulati, Syed Asrar ul Haq, Sumit Darak, Varun Singh:
Low-Complexity High Speed Residual Network-Augmented Channel Estimation for mmWave Massive MIMO. 56-60 - Yiheng Hui, Yuanlin Nong, He Ma, Jingjing Lv, Lei Chen, Li Du, Yuan Du:
A CNN-based One-shot Blind RX-side-only Equalization Scheme for High-speed SerDes links. 61-65 - Anitha Gopi, Elizabeth George, Rahul RK, Alex James:
AI for Antenna Design Re-engineering: Yes, Radiation Patterns Predict Antenna Structures! 66-70 - Kyudan Jung, Seungmin Bae, Nam Joon Kim, Jaepil Lim, Hyun Gon Ryu, Hyuk-Jae Lee:
Enhancing ASR Performance through Relative Word Frequency in OCR and Normal Word Frequency Analysis. 71-74 - Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis:
An end-to-end RNS CNN Accelerator. 75-79 - Cheng-Chen Lin, Wei Lu, Po-Tsang Huang, Hung-Ming Chen:
A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block. 80-84 - Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho:
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. 85-89 - Cheng-Yao Lo, Lean Karlo Santos Tolentino, Jhih-Ying Ke, Jeffrey S. Walling, Yang Yi, Chua-Chin Wang:
A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process. 90-94 - Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. 95-99 - Seongyon Hong, Sangyeob Kim, Soyeon Kim, Hoi-Jun Yoo:
DualNet: Efficient Integration of Artificial Neural Network and Spiking Neural Network with Equivalent Conversion. 100-104 - Nada AbuHamra
Memory-Centric Computing for Image Classification Using SNN with RRAM. 105-109 - Yazhuo Guo, Yuhan Qin, Song Chen, Yi Kang:
SPVT: Spiked Pyramid Vision Transformer. 110-113 - Harshiv Chandra
SNN-LIF Model for Glaucoma Classification. 114-118 - Aijaz H. Lone
Self-Resetting Magnetic Tunnel Junction Neuron-based Spiking Neural Networks. 119-123 - Pierangelo Maria Rapa, Mattia Orlandi, Andrea Amidei, Alessio Burrello, Roberto Rabbeni, Paolo Pavan
Driving Towards Safety: Online PPG-based Drowsiness Detection with TCNs. 124-128 - Livia Manovi, Lorenzo Capelli, Alex Marchioni, Filippo Martinini, Gianluca Setti, Mauro Mangia, Riccardo Rovatti:
SVD-based Peephole and Clustering to Enhance Trustworthiness in DNN Classifiers. 129-133 - Daniel Commey, Sena Hounsinou, Garth V. Crosby:
Strategic Deployment of Honeypots in Blockchain-based IoT Systems. 134-138 - Soheyb Ribouh, Abdenour Hadid:
Is Semantic Communication for Autonomous Driving Secured against Adversarial Attacks? 139-143 - Simon Wilhelmstätter, Joschua Conrad, Devanshi Upadhyaya, Ilia Polian, Maurits Ortmanns:
Attacking a Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models. 144-148 - Zekun Zhang, Yujie Cai, Tianjiao Liao, Chengyu Xu, Xin Jiao:
TENG: A General-Purpose and Efficient Processor Architecture for Accelerating DNN. 149-153 - Zilin Wang, Yi Zhong, Guang Chen, Shuo Feng, Youming Yang
A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array. 154-158 - Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos:
Reusing Softmax Hardware Unit for GELU Computation in Transformers. 159-163 - Jeongmin Shin, Hoichang Jeong, Seungbin Kim, Keonhee Park, Sangho Lee, Kyuho Lee
A Low-power 3D Point Clouds Matching Processor with 1D-CNN Prediction and CAM-based In-memory kNN Searching. 164-168 - Eman Hassan, Meriem Bettayeb, Baker Mohammad:
Advancing Hardware Implementation of Hyperdimensional Computing for Edge Intelligence. 169-173 - Minsang Yu, Minuk Hong, Sugil Lee, Seungsu Kim, Jongeun Lee:
PyAIM: Pynq-Based Scalable Analog In-Memory Computing Prototyping Platform. 174-178 - Haodong Han, Junpeng Wang, Bo Ding, Song Chen:
ILP-based Multi-Branch CNNs Mapping on Processing-in-Memory Architecture. 179-183 - Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta:
An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. 184-188 - Harideep Nair, David Barajas-Jasso, Quinn Jacobson, John Paul Shen:
TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning. 189-193 - DiDiego A. Silva, Ayan Shymyrbay, Kamilya Smagulova, Ahmed Elsheikh, Mohamed E. Fouda, Ahmed M. Eltawil
End-to-End Edge Neuromorphic Object Detection System. 194-198 - Cheol-Ho Choi, Joonhwan Han, Jeongwoo Cha, Jungho Shin, Hyun Woo Oh:
Fast Object Detection Algorithm using Edge-based Operation Skip Scheme with Viola-Jones Method. 199-203 - Hyunjun Ko, Jin-Ku Kang, Yongwoo Kim:
An Efficient and Fast Filter Pruning Method for Object Detection in Embedded Systems. 204-207 - Jiing-Ping Wang, Ming-Guang Lin, An-Yeu Andy Wu:
LATTE: Low-Precision Approximate Attention with Head-wise Trainable Threshold for Efficient Transformer. 208-212 - Zhijie Huang, Ao Qie, Chen Zhang, Jie Yang, Xin'an Wang:
Exploration for Efficient Depthwise Separable Convolution Networks Deployment on FPGA. 213-217 - Fatima Hameed Khan, Muhammad Adeel Pasha, Shahid Masud:
Exploring Memory Access Techniques for Efficient FPGA based 3D CNN Accelerator Design. 218-222 - Ayan Shymyrbay, Mohammed E. Fouda, Ahmed M. Eltawil
Towards Automated FPGA Compilation of Spiking Neural Networks. 223-227 - Léo Pradels, Silviu-Ioan Filip, Olivier Sentieys, Daniel Chillet, Thibaut Le Calloch:
FPGA-based CNN Acceleration using Pattern-Aware Pruning. 228-232 - Kasem Khalil, Tamador Mohaidat, Mahmoud Darwich, Ashok Kumar, Magdy A. Bayoumi:
Efficient Hardware Implementation of Artificial Neural Networks on FPGA. 233-237 - Vassilis Alimisis, Andreas Papathanasiou, Georgios Georgousis, Paul P. Sotiriadis:
An Analog Neural Network for Estimating Sea State or Wave Height from Inertial Sensor Data. 238-242 - Raphael Nägele, Jakob Finkbeiner, Markus Grözing, Manfred Berroth, Georg Rademacher:
Characterization of an Analog MAC Cell with Multi-Bit Resolution for AI Inference Accelerators. 243-247 - Kazybek Adam, Dipesh C. Monga
Evaluating an Analog Main Memory Architecture for All-Analog In-Memory Computing Accelerators. 248-252 - Jakob Finkbeiner, Raphael Nägele, Markus Grözing, Manfred Berroth, Georg Rademacher:
Characterization of a Femtojoule Voltage-to-Time Converter with Rectified Linear Unit Characteristic for Analog Neural Network Inference Accelerators. 253-257 - Alptekin Vardar, Franz Müller, Ipek Geçin, Nellie Laleni, Thomas Kämpfe:
Adaptive Mixed MLC-SLC FeFET Mapping for CIM AI Applications Through Simulated Annealing. 258-262 - Jingcun Wang, Bing Li, Grace Li Zhang:
Early-Exit with Class Exclusion for Efficient Inference of Neural Networks. 263-267 - Tsung-Lin Tsai, Yi-Cheng Lo, An-Yeu Andy Wu:
An Efficient Anomalous Sound Detection by Robust Processing and Reformation of Objective. 268-272 - Andriy Enttsel, Alex Marchioni, Gianluca Setti, Mauro Mangia, Riccardo Rovatti:
Enhancing Anomaly Detection with Entropy Regularization in Autoencoder-based Lightweight Compression. 273-277 - Shreya Kshirasagar, Benjamin Cramer, Andre Guntoro, Christian Mayr:
Auditory Anomaly Detection using Recurrent Spiking Neural Networks. 278-281 - Pavan Kumar MP, Zhe-Xiang Tu, Kun-Chih Jimmy Chen:
Fine-Tuned Based Transfer Learning with Temporal Attention and Physics-Informed Loss for Bearing RUL Prediction. 282-286 - Zhiyuan Xu, Xinyu Kang, Xingbo Wang, Bingzhen Chen, Terry Tao Ye:
FlexBits: A Configurable Lightweight RISC-V Micro-architecture for Flexible Bit-Width Execution. 287-291 - Bingzhen Chen, Xingbo Wang, Yucong Huang, Zhiyuan Xu:
RISCV-FNT: A Fast FNT-based RISC-V Processor for CNN Acceleration. 292-296 - Zhou Wang, Haochen Du, Baoyi Han, Yanqing Xu, Xiaonan Tang, Yang Zhou, Zhe Zheng, Wenpeng Cui, Yanwei Xiong, Shaojun Wei, Shushan Qiao, Shouyi Yin:
RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism. 297-301 - Zhou Wang, Haochen Du, Baoyi Han, Yanqing Xu, Xiaonan Tang, Yang Zhou, Zhe Zheng, Wenpeng Cui, Yanwei Xiong, Shaojun Wei, Shushan Qiao, Shouyi Yin:
RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism. 302-306 - Mincheol Cha, Keehyuk Lee, Xuan Truong Nguyen, Hyuk-Jae Lee:
A Low-Latency and Scalable Vector Engine with Operation Fusion for Transformers. 307-311 - Ziyang Shen, Xiaoxu Xie, Chaoming Fang, Fengshi Tian, Shunli Ma, Jie Yang, Mohamad Sawan:
NeuroSORT: A Neuromorphic Accelerator for Spike-based Online and Real-time Tracking. 312-316 - Yu-Hsuan Lin, Kea-Tiong Tang:
A 0.2-pJ/SOP Digital Spiking Neuromorphic Processor with Temporal Parallel Dataflow and Efficient Synapse Memory Compression. 317-321 - Jongkil Park, YeonJoo Jeong, Jaewook Kim, Suyoun Lee, Joon Young Kwak, Jong-Keuk Park, Inho Kim:
High-Density Digital Neuromorphic Processor with High-Precision Neural and Synaptic Dynamics and Temporal Acceleration. 322-326 - Arnob Saha, Bibhas Manna, Sen Lu, Zhouhang Jiang, Kai Ni, Abhronil Sengupta:
Device Feasibility Analysis of Multi-level FeFETs for Neuromorphic Computing. 327-331 - Guang Chen, Jian Cao, Shuo Feng, Zilin Wang, Yi Zhong, Qibin Li, Xiongbo Zhao, Xing Zhang, Yuan Wang:
On-Chip Incremental Learning based on Unsupervised STDP Implementation. 332-336 - Philippe Bich, Chiara Boretti, Luciano Prono, Fabio Pareschi, Riccardo Rovatti, Gianluca Setti:
Optimizing Vision Transformers: Leveraging Max and Min Operations for Efficient Pruning. 337-341 - Hangyul Choi, Seongmoon Jeong, Sangwoon Kwak, Soon-Heung Jung, Jong Hwan Ko:
Adaptive Image Downscaling for Rate-Accuracy-Latency Optimization of Task-Target Image Compression. 347-351 - Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim:
Fast, Efficient and Lightweight Compressed Image Super-Resolution Network for Edge Devices. 352-356 - Ying Tao, Chip-Hong Chang, Sylvain Saïghi, Shengyu Gao:
GaitSpike: Event-based Gait Recognition With Spiking Neural Network. 357-361 - Ming-Guang Lin, Jiing-Ping Wang, Cheng-Yang Chang, An-Yeu Andy Wu:
Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros. 362-366 - Shervin Vakili:
A Cost-Effective Baugh-Wooley Approximate Multiplier for FPGA-based Machine Learning Computing. 367-371 - Zhibin Luo, Junyi Mai, Enyi Yao:
OTFC-LSTM: An Efficient Design of LSTM Accelerator based on On-The-Fly CORDIC. 372-376 - Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Progressive Variable Precision DNN With Bitwise Ternary Accumulation. 377-381 - Rishi Agrawal, Narayanabhatla Savyasachi Abhijith, Uppugunduru Anil Kumar, Sreehari Veeramachaneni, Syed Ershad Ahmed:
Energy-Efficient Ternary Multiplier. 382-387 - Brady Taylor, Xiaoxuan Yang, Hai Li:
Weight Update Scheme for 1T1R Memristor Array Based Equilibrium Propagation. 388-392 - Sumit Diware, Mohammad Amin Yaldagard
Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks. 393-397 - Zhenming Yu, Ming-Jay Yang, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci:
The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming. 398-402 - Pierre Lewden
Effect of Line Resistance of Passive Memristive Crossbars on Spiking Neural Network Performance. 403-407 - Zidu Li, Phil David Börner, Maurice Müller, Andreas Bablich, Peter Haring Bolívar, Bhaskar Choubey:
Vibration may Break the Conductive Filament in amorphous Germanium based Memristor. 408-412 - Yichuan Bai, Xiaopeng Zhang, Qian Wang, Jingjing Lv, Lei Chen, Yuan Du, Li Du:
An Area-Efficient CNN Accelerator Supporting Global Average Pooling with Arbitrary Shapes. 413-416 - Kang Eun Jeon, Wooram Seo, Johnny Rhe, Jong Hwan Ko:
ConvMapSim: Modeling and Simulating Convolutional Weight Mapping for PIM Arrays. 417-421 - Zekun Zhang, Xin Jiao, Chengyu Xu:
A Feature Map Lossless Compression Framework for Convolutional Neural Network Accelerators. 422-426 - Nicolas Ramos, Hai Li:
CNN Implementation of Bayesian Plasticity for Robust Learning. 432-436 - Yu-Da Chu, Pei-Hsuan Kuo, Lyu-Ming Ho, Juinn-Dar Huang:
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems. 437-441 - Cédric Gernigon, Silviu-Ioan Filip, Olivier Sentieys, Clément Coggiola, Mickael Bruno:
AdaQAT: Adaptive Bit-Width Quantization-Aware Training. 442-446 - Xiangfeng Sun, Yuanting Zhang, Yunchang Jiang, Zheng Li, Bingjin Han, Junyi Mai, Zhibin Luo, Enyi Yao:
HLC: A Hardware-friendly Quantization and Cache-based Accelerator for Transformer. 447-451 - Zongcheng Yue, Ran Wu, Longyu Ma, Chong Fu, Chiu-Wing Sham:
PQDE: Comprehensive Progressive Quantization with Discretization Error for Ultra-Low Bitrate MobileNet towards Low-Resolution Imagery. 452-456 - Sangbeom Jeong, Dahun Choi, Hyun Kim:
SRU-Q: Hardware-friendly Stochastic Rounding Unit-based Gradient Quantization for CNN Training. 457-461 - Shreyas Deshmukh
Resistive Processing Unit-based On-chip ANN Training with Digital Memory. 462-466 - I-Chun Liu, Chun-Jui Chen, Xiu-Zhu Li, Yong-Qi Cheng, Chung-Wei Huang, Pin-Han Lin, Hsuan-Wei Pu, Sheng-Yu Peng, Yu Tsao:
The Multilayer Neural Network Implementation Using SRAM-Based Reconfigurable Cognitive Computation Matrices. 467-471 - Gilha Lee, Seungil Lee, Hyun Kim:
ACC: Adaptive Compression Framework for Efficient On-device CNN Training. 472-476 - Surajit Bhattacherjee, Daksh Shah, Dipankar Pal:
Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape. 477-481 - Bhaskar Choubey, Hendrik Sommerhoff, Michael Moeller, Andreas Kolb:
Variable layout CMOS pixels for end-to-end learning in task specific Image Sensors. 482-486 - Janak Sharda, Po-Kai Hsu, Shimeng Yu:
Accelerator Design using 3D Stacked Capacitorless DRAM for Large Language Models. 487-491 - Khaleelulla Khan Nazeer
Language Modeling on a SpiNNaker2 Neuromorphic Chip. 492-496 - Minseok Seo, Seongho Jeong, Hyuk-Jae Lee, Xuan Truong Nguyen:
Real Post-Training Quantization Framework for Resource-Optimized Multiplier in LLMs. 497-501 - You-En Wu, Hsin-I Wu, Kuo-Cheng Chin, Yi-Chun Yang, Ren-Song Tsay:
Accelerate Large Language Model Inference on Edge TPU with OpenVX framework. 502-506 - Salah Eddine Bekhouche, Abdenour Hadid:
Kinship Verification from Text: Towards Discovering Subtitle Textual Features Shared by Family Members using Large Language Models. 507-511 - Ruge Xu, Qiang Duan, Qibin Chen, Xinfei Guo:
ILD-MPQ: Learning-Free Mixed-Precision Quantization with Inter-Layer Dependency Awareness. 512-516 - Pietro Bonazzi, Yawei Li, Sizhen Bian, Michele Magno:
Q-Segment: Segmenting Images In-Sensor for Vessel-Based Medical Diagnosis. 517-521 - Juntao Guan, Gufeng Liu, Fanhong Zeng, Rui Lai, Ruixue Ding, Zhangming Zhu:
Microarchitecture Aware Neural Architecture Search for TinyML Devices. 522-526 - Huanan Li, Shicheng Jia, Juntao Guan, Rui Lai, Shubin Liu, Zhangming Zhu:
An Energy-Efficient Look-up Table Framework for Super Resolution on FPGA. 527-531 - Mohammad Kalbasi, Mohammad Ali Shaeri, Vincent Alexandre Mendez, Solaiman Shokur, Silvestro Micera, Mahsa Shoaran:
A Hardware-Efficient EMG Decoder with an Attractor-based Neural Network for Next-Generation Hand Prostheses. 532-536 - José Cubero-Cascante, Arunkumar Vaidyanathan, Rebecca Pelke, Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph:
A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars. 537-538 - Ming-Shan Huang, Pi-Chuan Chen, Tzi-Dar Chiueh:
TPC-NAS: Simple and Effective Neural Architecture Search Based on Total Path Count. 542-546 - Meriem Bettayeb, Eman Hassan, Muhammad Umair Khan
Adapting Spatial Transformer Networks Across Diverse Hardware Platforms: A Comprehensive Implementation Study. 547-551 - Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos:
Error Checking for Sparse Systolic Tensor Arrays. 552-556 - Joschua Conrad, Simon Wilhelmstätter, Rohan Asthana, Vasileios Belagiannis, Maurits Ortmanns:
Too-Hot-to-Handle: Insights into Temperature and Noise Hyperparameters for Differentiable Neural-Architecture-Searches. 557-561 - Lakshmi Iyer, Laxmeesha Somappa:
A 16-Channel GRU based On-Chip Seizure Classifier for Closed Loop Neuromodulation. 562-566 - Shijie Cheng, Ruifang Liu, Hao Wu, Keith Siu-Fung Sze, Qianjin Feng:
A Pulse Correlation Model for PPG Signal Quality Assessment and Key Pulse Extraction. 567-571 - Chanwook Hwang, Jaehyeon So
An Efficient Ventricular Arrhythmias Detection on Microcontrollers with Optimized 1D CNN. 572-576 - Yuhan Gu, Qing Wu, Zhechen Yuan, Xiangyu Zhang, Wenyan Su, Yuyao Zhang, Xin Lou:
An FPGA Accelerator for 3D Cone-beam Sparse-view Computed Tomography Reconstruction. 577-581 - Jie Lu, Guanghan Yu, Liyu Qian, Jiacheng Cao, Lirong Zheng, Zhuo Zou:
CS-Net: An End-to-end Network for Motor Imagery Brain-Machine Interface with Adaptive Channel Selection and Compressed Sensing. 582-586 - Pi-Chuan Chen, Yu-Tung Liu, Guo-Yang Zeng, Tzi-Dar Chiueh:
Design and Implementation of an Easy-to-Deploy Energy-Efficient Inference Acceleration System for Multi-Precision Neural Networks. 587-591 - Yuhan Qin, Yulong Meng, Haitao Du, Yazhuo Guo, Yi Kang:
MSCA: Model-Driven Search for Optimal Configuration for SpMM Accelerators. 592-596 - Hongbo Guo, Hao Wu, Jiahui Xia, Yibang Cheng, Qianhui Guo, Yi Chen, Tingyan Xu, Jiguang Wang, Guoxing Wang:
OSAHS Detection Capabilities of RingConn Smart Ring: A Feasibility Study. 597-601 - Ali Bazzi, Emmanuel Hardy, J. Ballester, Franck Badets, Louis Hutin:
Optimizing with phases: design and application space assessment for networks of phase-locked Ring Oscillators. 602-606 - Paulo Machado, Ruxandra Barbulescu, Luís Miguel Silveira:
Echo State Networks for Accurate and Efficient Modeling of Dynamic Circuits. 607-611
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-18 20:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: