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NORCAS 2019: Helsinki, Finland
- Jari Nurmi, Peeter Ellervee, Kari Halonen, Juha Röning:
2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019. IEEE 2019, ISBN 978-1-7281-2769-9 - Mohammad Amir Mansoori
, Mario R. Casu:
HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoC. 1-7 - Dmitry Osipov, Aleksandr Gusev, Steffen Paul, Vitaly Shumikhin:
Two-Step Pipeline SAR ADC with passive Charge Sharing between Cascades. 8138-8143 - Mikko Hietanen, Janne Aikio
Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI. 1-4 - Ruben Vazquez
Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded Systems. 1-7 - Jere Kekkonen, Ilkka Nissinen
Single Burst Depth-Resolving Raman Spectrometer Based on a SPAD Array with an On-Chip TDC to Analyse Heterogenous Liquid Samples. 1-5 - Mark G. Arnold, Ed Chester, John R. Cowles, Corey Johnson:
Optimizing Mitchell's Method for Approximate Logarithmic Addition via Base Selection with Application to Back-Propagation. 1-6 - Ayca Akkaya, Firat Celik, Yusuf Leblebici:
Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCs. 1-7 - Markus Mogensen Henriksen
A 500mV, 118nW, ∑Δ-Modulator ADC for Audio Detection in 28 nm FD-SOI. 1-6 - Azam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg:
Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications. 1-6 - Rana Azhar Shaheen, Timo Rahkonen, Rehman Akbar
Layout Optimization Techniques for $r_{g}$ and, $f_{max}$ of Cascode Devices for mm Wave Applications. 1-4 - Philipp Jungklass, Mladen Berekovic
MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements. 1-7 - Jere Rusanen
Ka-Band Stacked Power Amplifier on 22 nm CMOS FDSOI Technology Utilizing Back-Gate Bias for Linearity Improvement. 1-4 - Bardia Barabadi, Matthew Gara, Ali Jooya, Amirali Baniasadi, Nikitas Dimopoulos:
Dual-Stage Phase Unwrapping. 1-7 - Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet:
Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. 1-7 - Rui Ma
An Analogue Baseband Chain for a Magnetic Tunnel Junction Based RF Signal Detector. 1-6 - Marko Neitola:
Two-Stage Internal DAC Mismatch Mitigation for a Continuous-Time Delta-Sigma ADC. 1-7 - John Reuben
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. 1-6 - Arthur Silitonga, Zhou Jiang, Nadir Khan, Jürgen Becker:
Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs. 1-7 - Toshinori Sato
On Applications of Configurable Approximation to Irregular Voltage. 1-6 - Feridoon Jalili
Linearization of Active Transmitter Arrays in Presence of Antenna Crosstalk for 5G Systems. 1-5 - Dimitris Vordonis, Vassilis Paliouras
Sphere Decoder for Massive MIMO Systems. 1-6 - Alok Sethi, Rehman Akbar
Designing at Millimeter-Wave: Lessons from a Triple Coil Variable Transformer. 1-4 - Ahmet Cagri Bagbaba
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. 1-7 - Janne Koljonen
Fast Fixed-point Bicubic Interpolation Algorithm on FPGA. 1-7 - Lavanya Maddisetti
Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters. 1-6 - Taiki Nakanishi, Shunya Murakami, Atsuki Kobayashi, Md. Zahidul Islam
A 40-GHz Fully-Integrated CMOS-Based Biosensor Circuit with an On-Chip Vector Network Analyzer for Circulating Tumor Cells Analysis. 1-7 - Christopher H. K. Jensen, Rasmus B. Lind, Jens Christian Hertel, Ahmed M. Ammar
A Time-Based Control Scheme for Power Factor Correction Boost Converter. 1-6 - Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet:
Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. 1-6 - Panu Sjövall
Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud. 1-5 - Jakob Kenn Toft, Ivan H. H. Jørgensen:
Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology. 1-7 - Calvin Maxsen, Pere Llimós Muntal
A 36 nW trimless voltage reference with low sensitivity to PVT variations. 1-5 - Yuchen Zhao, Haoming Chu, Bengt Källbäck, Yajie Qin, Zhuo Zou, Lirong Zheng:
An AFE for Catheter-Based IEGM sensing with Inverter-based SAR ADC. 1-5 - Huanyu Wang, Martin Brisfors, Sebastian Forsmark, Elena Dubrova:
How Diversity Affects Deep-Learning Side-Channel Attacks. 1-7 - Emmanouil Kavvousanos, Vassilis Paliouras
Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes. 1-6 - Christos Gkiokas, Martin Schoeberl
A Fault-Tolerant Time-Predictable Processor. 1-6 - Zhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker:
Towards a Python-Based One Language Ecosystem for Embedded Systems Automation. 1-7 - Steinar Thune Christensen, Snorre Aunet, Omer Qadir:
A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks. 1-6 - Marko Neitola:
Practical Stimulus Design for a Multi-Tone Fit. 1-7 - Nico Angeli, Klaus Hofmann:
An All-Digital Duty-Cycle Corrector for Parallel High-Speed I/O Links. 1-6 - Jukka Peltomäki, Mengyang Chen, Heikki Huttunen
Semantic segmentation with inexpensive simulated data. 1-6 - Ricardo Núñez-Prieto
A Real-Time Gesture Recognition System with FPGA Accelerated ZynqNet Classification. 1-6 - Pedro Toledo, Orazio Aiello
A 300mV-Supply Standard-Cell-Based OTA with Digital PWM Offset Calibration. 1-5 - Hesam Zolfaghari, Davide Rossi, Jari Nurmi
An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. 1-7 - Jiri Blumenstein, Jiri Milos, Ladislav Polak
IEEE 802.11ad SC-PHY Layer Simulator: Performance in Real-world 60 GHz Indoor Channels. 1-4 - Rashid Ali, Maen Mallah, Martin Leyh, Philipp Holzinger
A Hardware Inference Accelerator for Temporal Convolutional Networks. 1-7 - Mohammadreza Nakhkash, Anil Kanduri, Amir M. Rahmani
End-to-End Approximation for Characterizing Energy Efficiency of IoT Applications. 1-6 - Simon Buhr, Martin Kreißig, Frank Ellinger:
A Real-Time Fast Ethernet Transceiver achieving Sub-ns Time Synchronization. 1-7 - Julián Caba
HALib: Hardware Assertion Library for on-board verification of FPGA-based modules using HLS. 1-7 - Siyu Tan, Lars Sundström
A 5 GHz CT $\Delta\sum$ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS. 1-4 - Lukas Straczek, Dominik J. Veit, Jürgen Oehm
1/f-Noise and Offset Cancellation for Rail-to-Rail Single-Slope ADCs in MEA Applications. 1-5 - Aneesh Balakrishnan
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. 1-7 - Saman Payvar, Esko Pekkarinen, Rafael Stahl, Daniel Mueller-Gritschneder
Instruction Extension of a RISC-V Processor Modeled with IP-XACT. 1-5 - Mostafa Jafari Nokandi, Sumit Pratap Singh, Aarno Pärssinen
A New Interpretation to Groszkowski's Effect. 1-4 - Emilio J. Martínez-Pérez
T-LINC Architecture with Digital Combination and Mismatch Correction in the Receiver. 1-5
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