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33rd MICRO 2000: Monterey, California, USA
- Andrew Wolfe, Michael S. Schlansker:
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000. ACM/IEEE Computer Society 2000, ISBN 0-7695-0924-x - David Baker:
A whole new ballgame - supercomputing on two AA batteries (keynote session). 3 - Darrell Boggs:
Breathing life into a paper tiger (keynote session). 5 - Phil Keukes:
Defect tolerant molecular electronics: algorithms, architectures, and atoms. 7 - Hsien-Hsin S. Lee
, Gary S. Tyson, Matthew K. Farrens:
Eager writeback - a technique for improving bandwidth utilization. 11-21 - Kevin M. Lepak, Mikko H. Lipasti:
Silent stores for free. 22-31 - Zhao Zhang, Zhichun Zhu, Xiaodong Zhang:
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. 32-41 - Timothy Sherwood
Predictor-directed stream buffers. 42-53 - Jared Stark, Mary D. Brown, Yale N. Patt:
On pipelining dynamic instruction scheduling logic. 57-66 - Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin:
The impact of delay on the design of branch predictors. 67-76 - Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson:
Improving BTB performance in the presence of DLLs. 77-86 - Saugata Chatterjee, Christopher T. Weaver, Todd M. Austin:
Efficient checker processor design. 87-97 - Alexandre E. Eichenberger, Waleed Meleis, Suman Maradani:
An integrated approach to accelerate data and predicate computations in hyperblocks. 101-111 - John W. Sias, Wen-mei W. Hwu, David I. August:
Accurate and efficient predicate analysis with binary decision diagrams. 112-123 - F. Jesús Sánchez, Antonio González:
Modulo scheduling for a fully-distributed clustered VLIW architecture. 124-133 - Javier Zalamea, Josep Llosa
Two-level hierarchical register file organization for VLIW processors. 137-146 - Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen:
PipeRench implementation of the instruction path coprocessor. 147-158 - Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany:
Efficient conditional operations for data-parallel architectures. 159-170 - Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man:
Flexible hardware acceleration for multimedia oriented microprocessors. 171-177 - Ramon Canal, Antonio González, James E. Smith:
Very low power pipelines using significance compression. 181-190 - J. Adam Butts, Gurindar S. Sohi:
A static power model for architects. 191-201 - Michael C. Huang
A framework for dynamic energy efficiency and temperature management. 202-213 - Luis Villa, Michael Zhang, Krste Asanovic:
Dynamic zero compression for cache energy reduction. 214-220 - Amir Roth, Gurindar S. Sohi:
Register integration: a simple and efficient implementation of squash reuse. 223-234 - Matt Postiff, David A. Greene, Trevor N. Mudge:
The store-load address table and speculative register promotion. 235-244 - Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. 245-257 - Jun Yang, Youtao Zhang, Rajiv Gupta
Frequent value compression in data caches. 258-265 - Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg:
A study of slipstream processors. 269-280 - Timothy H. Heil, James E. Smith:
Relational profiling: enabling thread-level parallelism in virtual machines. 281-290 - Markus Mock, Craig Chambers, Susan J. Eggers:
Calpa: a tool for automating selective dynamic compilation. 291-302 - Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum:
Increasing the size of atomic instruction blocks using control flow assertions. 303-313 - Joan-Manuel Parcerisa
Reducing wire delay penalty through value prediction. 317-326 - Eric Larson, Todd M. Austin:
Compiler controlled value prediction using branch predictor based confidence. 327-336 - Amirali Baniasadi, Andreas Moshovos:
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. 337-347 - Tong Liu, Shih-Lien Lu:
Performance improvement with circuit-level speculation. 348-355
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