default search action
MEMSYS 2019: Washington, DC, USA
- Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, Washington, DC, USA, September 30 - October 03, 2019. ACM 2019, ISBN 978-1-4503-7206-0
In-memory mechanisms
- Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf:
NEMESYS: near-memory graph copy enhanced system-software. 3-18 - Hoang Anh Du Nguyen, Jintao Yu
, Muath Abu Lebdeh
A computation-in-memory accelerator based on resistive devices. 19-32 - Jiwon Choe, Tali Moreshet, R. Iris Bahar
Attacking memory-hard scrypt with near-data-processing. 33-37 - Mohsen Imani, Saransh Gupta, Tajana Rosing:
Digital-based processing in-memory: a highly-parallel accelerator for data intensive applications. 38-40 - Jie Li
PIMS: a lightweight processing-in-memory accelerator for stencil computations. 41-52 - Ranjan Sarpangala Venkatesh
Fast in-memory CRIU for docker containers. 53-65
Errors, endurance, validation, resilience
- Darko Zivanovic, Pouya Esmaili-Dokht, Sergi Moré, Javier Bartolome, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé:
DRAM errors in the field: a statistical approach. 69-84 - Irina Alam, Saptadeep Pal, Puneet Gupta
Compression with multi-ECC: enhanced error resiliency for magnetic memories. 85-100 - Puneet Saraf, Madhu Mutyam:
Endurance enhancement of write-optimized STT-RAM caches. 101-113 - Brandon Nesterenko
Transitioning scientific applications to using non-volatile memory for resilience. 114-125 - Xiaoming Du, Cong Li
Combining error statistics with failure prediction in memory page offlining. 127-132 - Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn
Fast validation of DRAM protocols with timed petri nets. 133-147
Modeling & Optimization
- Edgar A. León, Brice Goglin, Andrès Rubio Proaño
M&MMs: navigating complex memory spaces with hwloc. 149-155 - Matthew Ben Olson
Portable application guidance for complex memory systems. 156-166 - Alif Ahmed, Kevin Skadron
Hopscotch: a micro-benchmark suite for memory performance evaluation. 167-172 - Louis Ye, Mieszko Lis, Alexandra Fedorova:
A unifying abstraction for data structure splicing. 173-183 - Shang Li, Rommel Sánchez Verdejo, Petar Radojkovic, Bruce L. Jacob:
Rethinking cycle accurate DRAM simulation. 184-191
Redesigning & rethinking systems
- Kazi Asifuzzaman
STT-MRAM for real-time embedded systems: performance and WCET implications. 195-205 - Sebastian Werner, Pouya Fotouhi
3D photonics as enabling technology for deep 3D DRAM stacking. 206-221 - Pouya Fotouhi
Enabling scalable chiplet-based uniform memory architectures with silicon photonics. 222-334 - Kyriakos Paraskevas
Scaling the capacity of memory systems; evolution and key approaches. 235-249 - Lars Schneidenbach, Bruce D'Amora, Claudia Misale, Carlos H. A. Costa, Sara Kokkila Schumacher
Data broker: a case for workflow enablement using a key/value approach. 250-260 - Arun Rodrigues, Maya B. Gokhale, Gwendolyn Voskuilen:
Towards a scatter-gather architecture: hardware and software issues. 261-271
Non-volatile main memories
- Daniel G. Waddington, Mark Kunitomi, Clem Dickey, Samyukta Rao, Amir Abboud, Jantz Tran:
Evaluation of intel 3D-xpoint NVDIMM technology for memory-intensive genomic workloads. 277-287 - Onkar Patil, Latchesar Ionkov, Jason Lee, Frank Mueller, Michael Lang:
Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules. 288-303 - Ivy Bo Peng
System evaluation of the Intel optane byte-addressable NVM. 304-315 - Byoungchan Oh
SMART: STT-MRAM architecture for smart activation and sensing. 316-330 - Xubin Chen, Yin Li, Jingpeng Hao, Hyunsuk Shin, Michael Suh, Tong Zhang:
Simultaneously reducing cost and improving performance of NVM-based block devices via transparent data compression. 331-341 - Meenatchi Jagasivamani, Candace Walden
Design for ReRAM-based main-memory architectures. 342-350
Memory-targeted compiler optimizations
- Daniel Byrne, Nilufer Onder, Zhenlin Wang:
Faster slab reassignment in memcached. 353-362 - Derrick Greenspan:
LLAMA - automatic memory allocations: an LLVM pass and library for automatically determining memory allocations. 363-372 - Muhammad M. Rafique, Zhichun Zhu:
FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM. 373-382 - T. Chad Effler, Brandon Kammerdiener, Michael R. Jantz
Evaluating the effectiveness of program data features for guiding memory management. 383-395 - Anup Sarma, Huaipan Jiang, Ashutosh Pattnaik, Jagadish Kotra, Mahmut Taylan Kandemir, Chita R. Das:
CASH: compiler assisted hardware design for improving DRAM energy efficiency in CNN inference. 396-407
Caching & cache techniques
- Dong Chen, Fangzhou Liu
Statistical caching for near memory management. 411-416 - Vamsee Reddy Kommareddy, Simon David Hammond, Clayton Hughes
Page migration support for disaggregated non-volatile memories. 417-427 - Luna Backes, Daniel A. Jiménez
The impact of cache inclusion policies on cache management techniques. 428-438 - Dhruv Gajaria
ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. 439-450 - Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang:
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. 451-458 - Ajitesh Srivastava, Angelos Lazaris, Benjamin Brooks, Rajgopal Kannan, Viktor K. Prasanna:
Predicting memory accesses: the road to compact ML-driven prefetcher. 461-470 - Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu
Inference engine benchmarking across technological platforms from CMOS to RRAM. 471-479 - Satyabrata Sen
Machine learning based design space exploration for hybrid main-memory design. 480-489 - Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. 490-496 - Zeshan Chishti, Berkin Akin:
Memory system characterization of deep learning workloads. 497-505 - Shaizeen Aga, Nuwan Jayasena, Mike Ignatowski:
Co-ML: a case for <u>co</u>llaborative <u>ML</u> acceleration using near-data processing. 506-517 - Shang Li, Bruce L. Jacob:
Statistical DRAM modeling. 521-530 - Randy Posey, Randall Burnett, Quentin Herr, Donald Miller:
Demonstration of superconducting memory with passive transmission line-based reads. 531-533
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-21 20:18 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: