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PACT 1995: Limassol, Cyprus
- Lubomir Bic, Paraskevas Evripidou, A. P. Wim Böhm, Jean-Luc Gaudiot:
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, PACT '95, Limassol, Cyprus, June 27-29, 1995. IFIP Working Group on Algol / ACM 1995 - Cindy Norris, Lori L. Pollock:
Register allocation sensitive region scheduling. 1-10 - Thomas S. Brasier, Philip H. Sweany, Steven J. Beaty, Steve Carr:
CRAIG: a practical framework for combining instruction scheduling and register assignment. 11-18 - David Bernstein, Doron Cohen, Ari Freund:
Compiler techniques for data prefetching on the PowerPC. 19-26 - Andrew Sohn, Chinhyun Kim, Mitsuhisa Sato:
Multithreading with the EM-4 distributed-memory multiprocessor. 27-36 - Masato Motomura, Toshiaki Inoue, Sunao Torii, Akihiko Konagaya:
Ordered multithreading: a novel technique for exploiting thread-level parallelism. 37-48 - Wayne Yamamoto, Mario Nemirovsky:
Increasing superscalar performance through multistreaming. 49-58 - Herbert H. J. Hum, Olivier Maquelin, Kevin B. Theobald, Xinmin Tian, Xinan Tang, Guang R. Gao, Phil Cupryk, Nasser Elmasri, Laurie J. Hendren, Alberto Jimenez, Shoba Krishnan, Andres Marquez, Shamir Merali, Shashank S. Nemawarkar, Prakash Panangaden, Xun Xue, Yingchun Zhu:
A design study of the EARTH multiprocessor. 59-68 - Jonas Skeppstedt, Per Stenström:
A compiler algorithm that reduces read latency in ownership-based cache coherence protocols. 69-78 - Nathalie Drach, André Seznec, Daniel Windheiser:
Direct-mapped versus set-associative pipelined caches. 79-88 - Adam R. Talcott, Mario Nemirovsky, Roger C. Wood:
The influence of branch prediction table interference on branch prediction scheme performance. 89-98 - Po-Yung Chang, Eric Hao, Yale N. Patt, Pohua P. Chang:
Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution. 99-108 - Pradeep K. Dubey, Kevin O'Brien, Kathryn M. O'Brien, Charles Barton:
Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grained multithreading. 109-121 - Lucas Roh, Walid A. Najjar:
Analysis of communications and overhead reduction in multithreaded execution. 122-130 - Bhanu Shankar, Lucas Roh, A. P. Wim Böhm, Walid A. Najjar:
Control of loop parallelism in multithreaded code. 131-139 - Eunha Rho, Sang Yong Han, Heunghwan Kim, Daejoon Hwang:
Effects of data bundling in non-strict data structures. 140-148 - Patricia Prather Pineo, Mary Lou Soffa:
Practical approach to single assignment code. 149-158 - Michel Cosnard, Michel Loi:
A simple algorithm for the generation of efficient loop structures. 159-167 - Jürgen Vollmer:
Data flow analysis of parallel programs. 168-177 - Mayez Al-Mouhamed, Adel Al-Maasarani:
Scheduling optimization through iterative refinement. 178-184 - Catherine Mongenet:
Mappings for communication minimization using distribution and alignment. 185-193 - David H. Albonesi, Israel Koren:
An analytical model of high performance superscalar-based multiprocessors. 194-203 - Evan Torrie, Chau-Wen Tseng, Margaret Martonosi, Mary W. Hall:
Evaluating the impact of advanced memory systems on compiler-parallelized codes. 204-213 - Thomas L. Sterling, Daniel Savarese, Phillip Merkey, Kevin Olson:
An empirical evaluation of the Convex SPP-1000 hierarchical shared memory system. 214-223 - Dean Engelhardt, Andrew L. Wendelborn:
A partitioning-independent paradigm for nested data parallelism. 224-233 - Y. Robin:
IPF for real-time image processing on massively parallel architectures. 234-243 - Siegfried Benkner:
Handling block-cyclic distributed arrays in Vienna Fortran 90. 244-253 - Abdou Youssef:
Translation of serial recursive codes to parallel SIMD codes. 254-263 - Christine Eisenbeis, Sylvain Lelait, Bruno Marmol:
The meeting graph: a new model for loop cyclic register allocation. 264-267 - Kanad Roy, Carl McCrosky:
Transformation of functional specifications of finite difference methods to parallel distributed codes. 268-272 - Rainer Leupers, Peter Marwedel:
Using compilers for heterogeneous system design. 273-276 - Jian Wang, Andreas Krall, M. Anton Ertl:
Decomposed software pipelining with reduced register requirement. 277-280 - Rudolph N. Rechtschaffen, Kattamuri Ekanadham:
Self-parallelization of sequential object codes. 281-283 - Teruaki Kitasuka, Kazuki Joe, Dale Schouten, Akira Fukuda, Keijiro Araki:
A loop parallelization technique for linear dependence vector. 285-289 - Christine Eisenbeis, Franco Gasperoni, Uwe Schwiegelshohn:
Allocating registers in multiple instruction-issuing processors. 290-293 - Soo-Mook Moon:
Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical code. 294-297 - Shin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, Shinji Tomita:
A proposal of self-cleanup cache. 298-301 - Bryce Cogswell, Zary Segall:
Performance impact of architectural features during binary to binary translation. 302-305 - Cristina Barrado, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Automatic generation of loop scheduling for VLIW. 306-309 - Elena Trichina:
From functional equations to Occam programs: systolizing compilation. 310-314
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