Category:Computer buses
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In computer architecture, a bus (a contraction of the Latin omnibus) is a communication system, that transfers data between components inside a computer, or between computers. This expression covers all related hardware components (wire, optical fiber, etc.) and software, including communication protocols.
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system that transfers data between components within a computer | |||||
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Said to be the same as | Q12576699 | ||||
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Subcategories
This category has the following 86 subcategories, out of 86 total.
A
B
C
- CAMAC (4 F)
D
E
F
G
H
- HIL bus (4 F)
- Hyper Transport (1 F)
I
K
L
- LocalTalk (9 F)
M
- MBus (SPARC) (5 F)
- MIL-STD-1553 (28 F)
N
P
Q
S
- SLIMbus (3 F)
- SlimPort (4 F)
- SmartSlot cards (5 F)
- SS-50 bus (3 F)
- STEbus (8 F)
T
- T-Bus (10 F)
- TURBOchannel (3 F)
V
- VPX (3 F)
W
X
Media in category "Computer buses"
The following 62 files are in this category, out of 62 total.
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20mA-Schnittstelle.png 660 × 350; 23 KB
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Amsterdam RAI METS 2011 (089).JPG 1,877 × 1,665; 839 KB
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Atari XL PBI and XE ECI.png 2,800 × 1,764; 6.32 MB
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ATCA Shelf Manager.jpg 2,592 × 2,076; 444 KB
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BA213.jpg 682 × 800; 123 KB
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Bus And Tag.jpg 902 × 600; 152 KB
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Bus parallelo.png 376 × 138; 2 KB
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Bust transfer.png 412 × 149; 2 KB
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Cnr.jpg 368 × 124; 28 KB
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CoCo3system.jpg 1,166 × 808; 449 KB
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Collegamento CMOS a bus con uscite 3S.png 164 × 264; 1 KB
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Commslot1.jpg 2,560 × 1,712; 2.04 MB
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CompSAN 2.GIF 890 × 620; 39 KB
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CompSAN.png 841 × 640; 29 KB
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CompSAN3.png 976 × 734; 32 KB
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Computer buses.svg 1,024 × 350; 8 KB
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Conn idc20m.svg 125 × 52; 14 KB
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Connection CMOSes to bus through OC outputs.png 151 × 237; 900 bytes
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CPT-3Box-Model-Peripherals.svg 680 × 604; 20 KB
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CPT-3Box-Model.svg 686 × 277; 14 KB
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D6708 CloseUp.png 166 × 183; 53 KB
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Esempio di arbitraggio del bus.png 228 × 307; 2 KB
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FlexRay Frame.svg 512 × 157; 136 KB
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Flexray.svg 800 × 500; 39 KB
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Flexrayframe.png 463 × 248; 14 KB
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Fpdaq1616-dimensions.jpg 500 × 319; 134 KB
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Geographical addressing.png 139 × 161; 690 bytes
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GIO EISA.jpg 900 × 246; 76 KB
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Ind Req.jpg 329 × 144; 6 KB
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Indirizzamento codificato.png 376 × 250; 2 KB
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Intercpunetbus.png 183 × 65; 5 KB
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IWS bus connection topology.png 406 × 160; 2 KB
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Linear addressing mode.png 231 × 139; 763 bytes
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Logical addressing.png 139 × 138; 735 bytes
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Wv-ZFA-Schema.jpg 794 × 1,123; 52 KB
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Modem sincrono.png 668 × 170; 2 KB
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Motherboard bus.jpg 1,024 × 683; 377 KB
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Mpi bk.jpg 800 × 517; 64 KB
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MT-32 f gen.svg 456 × 282; 191 KB
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N2K-CABLING.jpg 3,072 × 2,304; 2.54 MB
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NMEA2000 Modified motor yacht.jpg 1,903 × 928; 391 KB
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PCIe104 SAMMIT.jpg 1,219 × 1,303; 220 KB
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PCIe104 SAMMIT1.jpg 1,219 × 1,303; 186 KB
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Pisa connector.jpg 2,565 × 972; 709 KB
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PNT Layer2.jpg 553 × 207; 24 KB
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PNT Layer3.jpg 506 × 169; 15 KB
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RS-232 DE-9 Connector Pinouts.png 1,010 × 358; 34 KB
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RS-232 Pinouts for the DE-9 Connector.svg 512 × 221; 43 KB
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RS-422-423 449 pinout.png 669 × 553; 10 KB
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RX-generated single clock.png 308 × 158; 864 bytes
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SBC-Backplane.jpg 1,280 × 835; 205 KB
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Serial transmission rate.png 211 × 152; 1 KB
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SM1425-MPI.jpg 3,103 × 1,916; 748 KB
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SS30 BUS.jpg 683 × 512; 78 KB
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ST-506 MFM Twin Cables.xcf 1,796 × 1,320; 6.75 MB
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Standard Bus.JPG 482 × 229; 16 KB
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Topologia a bus.png 322 × 138; 1 KB
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TX-generated single clock.png 308 × 158; 844 bytes
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Wishbone Interface.png 343 × 324; 16 KB
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Межмодульный параллельный интерфейс.jpg 1,771 × 855; 388 KB