CT 122: INTORDUCTION TO

COMPUTER ENGINEERING

LECTURE 2
A TOP-LEVEL VIEW OF COMPUTER
FUNCTION AND INTERCONNECTION

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 Introduction
At a top level, a computer consists of CPU (central processing unit),
memory, and I/O components, with one or more modules of each
type.
These components are interconnected in some fashion to achieve
the basic function of the computer, which is to execute programs.
Thus, at a top level, a computer system can be described by:
1) describing the external behavior of each component—that is,
the data and control signals that it exchanges with other
components
2) describing the interconnection structure and the controls
required to manage the use of the interconnection structure.
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 COMPUTER COMPONENTS
Virtually all contemporary computer designs are based on
concepts developed by John von Neumann.
Such a design is referred to as the von Neumann architecture
and is based on three key concepts:
 Data and instructions are stored in a single read–write
memory.
 The contents of this memory are addressable by location,
without regard to the type of data contained there.
 Execution occurs in a sequential fashion from one instruction
to the next.
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 COMPUTER COMPONENTS cont…
The CPU module exchanges data with memory.
For this purpose, it typically makes use of internal (to the
CPU) registers:
 a memory address register (MAR), which specifies the
address in memory for the next read or write, and
 a memory buffer register (MBR), which contains the data to
be written into memory or receives the data read from
memory
 an I/O address register (I/OAR) specifies a particular I/O
device.
 an I/O buffer (I/OBR) register is used for the exchange of
4 data between an I/O module and the CPU.
 COMPUTER COMPONENTS cont…
A memory module consists of a set of locations,
defined by sequentially numbered addresses.
 Each location contains a binary number that can be
interpreted as either an instruction or data.
An I/O module transfers data from external
devices(peripherals) to CPU and memory, and vice
versa.
 It contains internal buffers for temporarily holding
these data until they can be sent on.
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 Computer Components: Top-Level View

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 COMPUTER FUNCTION
The basic function performed by a computer is execution of a
program, which consists of a set of instructions stored in
memory.
The processor does the actual work by executing instructions
specified in the program.
This section provides an overview of the key elements of
program execution.
In its simplest form, instruction processing consists of two
steps: the processor reads ( fetches) instructions from memory
one at a time and executes each instruction.
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 COMPUTER FUNCTION cont…
The processing required for a single instruction is
called an instruction cycle.
The two steps are referred to as the fetch cycle and the
execute cycle.
Program execution halts only if the machine is turned
off, some sort of unrecoverable error occurs, or a
program instruction that halts the computer is
encountered.

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 Basic Instruction Cycle

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 COMPUTER FUNCTION cont…
Instruction Fetch and Execute
At the beginning of each instruction cycle, the processor
fetches an instruction from memory.
In a typical processor, a register called the program counter
(PC) holds the address of the instruction to be fetched next.
Unless told otherwise, the processor always increments the PC
after each instruction fetch so that it will fetch the next
instruction in sequence (i.e., the instruction located at the next
higher memory address).

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 COMPUTER FUNCTION cont…
The fetched instruction is loaded into a register in the
processor known as the instruction register (IR).
The instruction contains bits that specify the action the
processor is to take: the processor interprets the instruction
and performs the required action.
In general, these actions fall into four categories:
 Processor-memory: Data may be transferred from processor
to memory or from memory to processor.
 Processor-I/O: Data may be transferred to or from a
peripheral device by transferring between the processor and
an I/O module.
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 COMPUTER FUNCTION cont…
 Data processing: The processor may perform some
arithmetic or logic operation on data.
 Control: An instruction may specify that the sequence of
execution be altered.
For example, the processor may fetch an instruction from
location 149, which specifies that the next instruction be
from location 182. The processor will remember this fact by
setting the program counter to 182. Thus, on the next fetch
cycle, the instruction will be fetched from location 182
rather than 150.

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 COMPUTER FUNCTION cont…
For example, consider the instruction, expressed symbolically
as ADD B,A, that stores the sum of the contents of memory
locations B and A into memory location A.
A single instruction cycle with the following steps occurs:
1. Fetch the ADD instruction.
2. Read the contents of memory location A into the processor.
3. Read the contents of memory location B into the processor.
4. Add the two values.
5. Write the result from the processor to memory location A.

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 COMPUTER FUNCTION cont…
Thus, the execution cycle for a particular instruction may
involve more than one reference to memory.
Also, instead of memory references, an instruction may
specify an I/O operation.
With these additional considerations in mind, provides a more
detailed look at the basic instruction cycle.
For any given instruction cycle, some states may be null and
others may be visited more than once.
The states can be described as follows:

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 COMPUTER FUNCTION cont…
Instruction address calculation (iac): Determine the address
of the next instruction to be executed.
Instruction fetch (if): Read instruction from its memory
location into the processor.
Instruction operation decoding (iod): Analyze instruction to
determine type of operation to be performed and operand(s) to
be used.
Operand address calculation (oac): If the operation involves
reference to an operand in memory or available via I/O, then
determine the address of the operand.
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 COMPUTER FUNCTION cont…
Operand fetch (of): Fetch the operand from memory
or read it in from I/O.
Data operation (do): Perform the operation indicated
in the instruction.
Operand store (os): Write the result into memory or
out to I/O.

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 Instruction Cycle State Diagram

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 COMPUTER FUNCTION cont…
States in the upper part involve an exchange between the
processor and either memory or an I/O module.
States in the lower part of the diagram involve only internal
processor operations.
The oac state appears twice, because an instruction may
involve a read, a write, or both.
However, the action performed during that state is
fundamentally the same in both cases, and so only a single
state identifier is needed.

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 Interrupts
Virtually all computers provide a mechanism by which other
modules (I/O, memory) may interrupt the normal processing of
the processor: these are classes of interrupts
The following table lists the most common classes of interrupts.

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 INTERRUPTS AND THE INSTRUCTION CYCLE
With interrupts, the processor can be engaged in executing
other instructions while an I/O operation is in progress.

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 INTERRUPTS AND THE INSTRUCTION CYCLE …
In the interrupt cycle, the processor checks to see if
any interrupts have occurred, indicated by the
presence of an interrupt signal.
If no interrupts are pending, the processor proceeds to
the fetch cycle and fetches the next instruction of the
current program.

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 INTERRUPTS AND THE INSTRUCTION CYCLE…
If an interrupt is pending, the processor does the following:
It suspends execution of the current program being
executed and saves its context.
It sets the program counter to the starting address of an
interrupt handler routine.
The processor now proceeds to the fetch cycle and fetches
the first instruction in the interrupt handler program, which
will service the interrupt.
The interrupt handler program is generally part of the
operating system.

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 Instruction Cycle State Diagram, with Interrupts

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 INTERCONNECTION STRUCTURES
A computer consists of a set of components or modules of
three basic types (processor, memory, I/O) that communicate
with each other.
In effect, a computer is a network of basic modules.
Thus, there must be paths for connecting the modules.
The collection of paths connecting the various modules is
called the interconnection structure.
The design of this structure will depend on the exchanges that
must be made among modules.

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 Bits, Bytes and Words
Bit: is the smallest unit of measurement used to quantify
computer data. It contains a single binary value of 0 or 1.
Byte: Sequence of eight bits. Therefore, each byte can be used
to represent 256 different values.
Word: Sequence of M-bits or collection of bits specified as a
single unit. The word may be as long as 64 bits or as short as 8
bits. Some memory units are not made up of bytes but of
words.
NB: Generally, files, storage devices, and storage capacity are measured in bytes, while
data transfer rates are measured in bits. For instance, an SSD may have a storage capacity
of 240 GB, while a download may transfer at 10 Mbps. Additionally, bits are also used to
describe processor architecture, such as a 32-bit or 64-bit processor.

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 Computer Modules
Memory: Typically, a memory module will consist of N
words of equal length.
Each word is assigned a unique numerical address (0,
1, . . . ,N – 1).
 A word of data can be read from or written into the
memory.
The nature of the operation is indicated by read and
write control signals: The location for the operation is
specified by an address.
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 Computer Modules cont…

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 Computer Modules cont…
I/O module: From an internal point of view, I/O is functionally
similar to memory.
There are two operations, read and write.
An I/O module may control more than one external device.
We can refer to each of the interfaces to an external device as a port
and give each a unique address (e.g., 0, 1, . . . ,M– 1).
In addition, there are external data paths for the input and output
of data with an external device.
An I/O module may be able to send interrupt signals to the
processor.

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 Computer Modules cont…

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 Computer Modules cont…
Processor: The processor reads in instructions and data, writes out
data after processing, and uses control signals to control the overall
operation of the system.
It also receives interrupt signals.

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 INTERCONNECTION STRUCTURES cont…
 The interconnection structure must support the following types of
transfers:
 Memory to processor: The processor reads an instruction or a unit of
data from memory.
 Processor to memory: The processor writes a unit of data to memory.
 I/O to processor:The processor reads data from an I/O device via an
I/O module.
 Processor to I/O: The processor sends data to the I/O device.
 I/O to or from memory: For these two cases, an I/O module is
allowed to exchange data directly with memory, without going
through the processor, using direct memory access (DMA).

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 BUS INTERCONNECTION
A bus is a communication pathway connecting two or more
devices.
A key characteristic of a bus is that it is a shared
transmission medium.
Multiple devices connect to the bus, and a signal transmitted
by any one device is available for reception by all other
devices attached to the bus.
If two devices transmit during the same time period, their
signals will overlap and become garbled: thus, only one device
at a time can successfully transmit.
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 Bus Structure
A bus consists of multiple communication pathways, or lines, each
line is capable of transmitting signals representing binary 1 and
binary 0.
A bus that connects major computer components (processor,
memory, I/O) is called a system bus.
The most common computer interconnection structures are based
on the use of one or more system buses.
On any bus the lines can be classified into three functional groups:
data, address, and control lines.
In addition, there may be power distribution lines that supply
power to the attached modules.
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 Bus Structure cont…
The data lines provide a path for moving data among system
modules: these lines, collectively, are called the data bus.
The data bus may consist of 32, 64, 128, or even more separate lines,
the number of lines being referred to as the width of the data bus.
Because each line can carry only 1 bit at a time, the number of lines
determines how many bits can be transferred at a time.
The width of the data bus is a key factor in determining overall
system performance.
For example, if the data bus is 32 bits wide and each instruction is
64 bits long, then the processor must access the memory module
twice during each instruction cycle.
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 Bus Structure cont…
The address lines are used to designate the source or
destination of the data on the data bus.
For example, if the processor wishes to read a word (8, 16, or
32 bits) of data from memory, it puts the address of the desired
word on the address lines.
The width of the address bus determines the maximum
possible memory capacity of the system.
Furthermore, the address lines are generally also used to
address I/O ports.

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 Bus Structure cont…
The control lines are used to control the access to and the use
of the data and address lines.
Because the data and address lines are shared by all
components, there must be a means of controlling their use.
Control signals transmit both command and timing
information among system modules.
Timing signals indicate the validity of data and address
information.
Command signals specify operations to be performed.

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 Bus Structure cont…
 Typical control lines include
 Memory write: Causes data on the bus to be written into the addressed
location
 Memory read: Causes data from the addressed location to be placed
on the bus
 I/O write: Causes data on the bus to be output to the addressed I/O
port
 I/O read: Causes data from the addressed I/O port to be placed on the
bus
 Transfer ACK: Indicates that data have been accepted from or placed
on the bus

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 Bus Structure cont…
Bus request: Indicates that a module needs to gain control of
the bus
 Bus grant: Indicates that a requesting module has been
granted control of the bus
Interrupt request: Indicates that an interrupt is pending
Interrupt ACK: Acknowledges that the pending interrupt
has been recognized
 Clock: Is used to synchronize operations
Reset: Initializes all modules

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 Bus Interconnection Scheme

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 Bus Structure cont…
The operation of the bus is as follows:
 If one module wishes to send data to another, it must do two
things:
(1) obtain the use of the bus
(2) transfer data via the bus.
 If one module wishes to request data from another module, it
must:
(1) obtain the use of the bus
(2) transfer a request to the other module over the appropriate
control and address lines.
 It must then wait for that second module to send the data.
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 Multiple-Bus Hierarchies
If a great number of devices are connected to the bus,
performance will suffer.
There are two main causes:
1. In general, the more devices attached to the bus, the greater
the bus length and hence the greater the propagation delay.
 This delay determines the time it takes for devices to
coordinate the use of the bus.
 When control of the bus passes from one device to another
frequently, these propagation delays can noticeably affect
performance.
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 Multiple-Bus Hierarchies
2.The bus may become a bottleneck as the aggregate
data transfer demand approaches the capacity of the
bus.
 This problem can be countered to some extent by
increasing the data rate that the bus can carry and by
using wider buses (e.g., increasing the data bus from
32 to 64 bits).

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 Traditional bus architecture
The traditional bus connection uses three buses
local bus , system bus and expansion bus
1. Local bus connects the processor to cache
memory and may support one or more local devices
2. The cache memory controller connects the cache
to local bus and to the system bus.
3. System bus also connects main memory module
4. Input /output transfer to and from the main
memory across the system bus do not interface with
the processor activity because process accesses cache
memory.
5. It is possible to connect I/O controllers directly on
to the system bus. A more efficient solution is to
make use of one or more expansion buses for this
purpose. An expansion bus interface buffers data
transfer between system bus and i/o controller on
the expansion bus.
This arrangement allows the system to support a
wide variety of i/o devices and at the same time
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insulate memory to process or traffic from i/o
traffic.
 High-performance architecture
The traditional bus connection uses three buses
local bus , system bus, expansion bus and high-
speed bus
1. Similar to the previous arrangement, there is a
local bus that connects the processor to a cache
controller, which is, in turn, connected to a system
bus that supports the main memory.
2. The cache controller is integrated into a bridge
or buffering device that connects to a high-speed
bus.
3. This (High Speed) bus supports connections to
high-speed LANs, such as Fast Ethernet at 100
Mbps, video and graphics workstation controllers
to local peripheral busses, including SCSI and
Firewire.
4. An expansion bus still supports lower-speed
devices, with an interface buffering traffic
between the expansion bus and the high-speed
44 bus.
 Elements of Bus Design

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 Elements of Bus Design cont…
BUS TYPES
Bus lines can be separated into two generic types: dedicated
and multiplexed.
A dedicated bus line is permanently assigned either to one
function (e.g. address bus) or to a physical subset of
computer components (e.g. I/O bus connects all I/O
modules).
The method of using the same lines for multiple purposes
(e.g. a bus can be used for both addresses and data) is
known as time multiplexing.
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 Elements of Bus Design cont…
METHOD OF ARBITRATION
Bus arbitration is a process by which next device becomes the
bus controller by transferring bus mastership to another bus.
In a centralized scheme, a single hardware device, referred
to as a bus controller or arbiter, is responsible for allocating
time on the bus.
The device may be a separate module or part of the
processor.
In a distributed scheme, there is no central controller, rather,
each module contains access control logic and the modules
47 act together to share the bus.
 Elements of Bus Design cont…
TIMING
Timing refers to the way in which events are coordinated on the
bus.
Buses use either synchronous timing or asynchronous timing.
With synchronous timing, the occurrence of events on the bus is
determined by a clock.
The bus includes a clock line upon which a clock transmits a
regular sequence of alternating 1s and 0s of equal duration.
With asynchronous timing, the occurrence of one event on a bus
follows and depends on the occurrence of a previous event.

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 Elements of Bus Design cont…
BUS WIDTH
The wider the data bus, the greater the number of bits
transferred at one time.
The width of the address bus has an impact on system
capacity: the wider the address bus, the greater the
range of locations that can be referenced.

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 Elements of Bus Design cont…
DATA TRANSFER TYPE
All buses support both write (master to slave) and read (slave to master)
transfers.
A read–modify–write operation is simply a read followed immediately
by a write to the same address.
Read-after-write is an indivisible operation consisting of a write followed
immediately by a read from the same address. The read operation may be
performed for checking purposes.
Some bus systems also support a block data transfer: In this case, one
address cycle is followed by n data cycles. The first data item is
transferred to or from the specified address; the remaining data items are
transferred to or from subsequent addresses.
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 PCI (Peripheral Component Interconnect)
The peripheral component interconnect (PCI) is a popular
high-bandwidth, processor-independent bus that can function
as a peripheral bus.
Compared with other common bus specifications, PCI delivers
better system performance for high-speed I/O subsystems
(e.g., graphic display adapters, network interface controllers,
disk controllers, and so on).
PCI is specifically designed to meet economically the I/O
requirements of modern systems; it requires very few chips to
implement and supports other buses attached to the PCI bus.
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 PCI cont…
PCI is designed to support a variety of
microprocessor-based configurations, including both
single- and multiple-processor systems.
Accordingly, it provides a general-purpose set of
functions.
It makes use of synchronous timing and a centralized
arbitration scheme.

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 Example PCI Configurations: Typical desktop system

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 PCI cont…
The above figure shows a typical use of PCI in a
single-processor system.
A combined DRAM controller and bridge to the PCI
bus provides tight coupling with the processor and the
ability to deliver data at high speeds.
The bridge acts as a data buffer so that the speed of
the PCI bus may differ from that of the processor’s I/O
capability.

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 Example PCI Configurations: Typical server system

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 PCI cont…
In a multiprocessor system, one or more PCI
configurations may be connected by bridges to the
processor’s system bus.
The system bus supports only the processor/cache
units, main memory, and the PCI bridges.
Again, the use of bridges keeps the PCI independent
of the processor speed yet provides the ability to
receive and deliver data rapidly.

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 Bus Structure
PCI may be configured as a 32- or 64-bit bus.
These are divided into the following functional groups:
System pins: Include the clock and reset pins.
Address and data pins: Include 32 lines that are time
multiplexed for addresses and data. The other lines in this
group are used to interpret and validate the signal lines that
carry the addresses and data.
Interface control pins: Control the timing of transactions
and provide coordination among initiators and targets.

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 Bus Structure cont…
Arbitration pins: Unlike the other PCI signal lines, these are
not shared lines. Rather, each PCI master has its own pair of
arbitration lines that connect it directly to the PCI bus arbiter.
Error reporting pins: Used to report parity and other errors.
Interrupt pins: These are provided for PCI devices that must
generate requests for service. As with the arbitration pins,
these are not shared lines. Rather, each PCI device has its
own interrupt line or lines to an interrupt controller.

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 Bus Structure cont…
 Cache support pins: These pins are needed to support a memory on
PCI that can be cached in the processor or another device. These pins
support snoopy cache protocols (see Chapter 18 for a discussion of
such protocols).
 64-bit bus extension pins: Include 32 lines that are time multiplexed
for addresses and data and that are combined with the mandatory
address/data lines to form a 64-bit address/data bus. Other lines in
this group are used to interpret and validate the signal lines that carry
the addresses and data. Finally, there are two lines that enable two PCI
devices to agree to the use of the 64-bit capability.
 JTAG/boundary scan pins: These signal lines support testing
procedures defined in IEEE Standard 1149.1.
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 Data transfer
Every data transfer on the PCI bus is a single transaction consisting
of one address phase and one or more data phases.

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 PCI Commands
 Interrupt Acknowledge
 Special Cycle
 I/O Read
 I/O Write
 Memory Read
 Memory Read Line
 Memory Read Multiple
 Memory Write
 Memory Write and Invalidate
 Configuration Read
 Configuration Write
 Dual address Cycle

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