Chapter 2.1 The 8086 Microprocessor Architecture

Department of Electrical and computer Engineering
College of Engineering and Technology

Jimma University
CHAPTER 2.1
ARCHITECTURE OF 8086
MICROPROCESSOR
CHAPTER OBJECTIVE
 Be familiar with the 8086
microprocessors architecture
Its general features
Its register architecture
Its memory segmentation
ETC
2
FEATURE OF 8086
 This is the photo of the
microprocessor
3
INTRODUCTION TO 8086
MICROPROCESSOR
4
FEATURE 8086 MICROPROCESSOR
5
GENERAL FEATURE OF 8086
 8086 was introduced in 1978 G.C. by Intel.
 It is 40 pin dual in line packaged
 Use high-performance metal-oxide
semiconductor (HMOS) technology
 It has approximately 29,000 transistors
6
INTERNAL ARCHITECTURE OF
8086
 It is a 16 bit microprocessor (16 bit word
length)
 The ALU work 16 bit at a time
 Has 16 bit register sets
 Has16 bit internal and external data bus
 Memory
 Ports
 Address space
 20 bit address bus (can access 2 2oor 1mb)
 16 bit Input and output address space (can
access 216 location of ports)
7
ARCHITECTURE OF
8086(CONTI…)
 It has 14, 16 bit register sets
 Can operate in two modes
Minimum mode(single processor application)
Maximum mode(multiple processor
application)
 Has different addressing modes
Register addressing mode
Immediate addressing modes
Direct addressing modes
Etc
8
ARCHITECTURE OF
8086(CONTI…)
 Internal it has two functional units
The bus interface unit(BIU)
The execution unit
 These functional unit can work
simultaneously increasing the
number of instruction executed per
unit time (Pipelining)
9
10
THE BUS INTERFACING
UNIT(BIU)
 Function of the BIU
 8086 interface to the outside world through the
BIU
 It provides 16 bit data bus and 20 bit address bus
 Some of its functions includes
 Fetching instruction from memory
 Reading and writing data to memory or IO ports
 It queue (pre-fetch) instruction for the 8086 the
purpose of pipeline
 It calculate the physical or effective address of a
memory
11
THE BUS INTERFACING
UNIT(BIU)
 Component of the BIU
The instruction queues
 Speed up program execution
 Pre-fetch 6 byte of instruction in
queue registers
Segment registers
Instruction pointer
Bus control logic
Address summer
12
THE EXECUTION UNIT(EU)
 Tells the address of the instruction and data
that it want to access to the BIU
 It decode and execute instructions
 Part of the EU includes
 Control unit
 Arithmetic and logic unit (ALU)
 Set of registers
 General purpose registers
 Pointers and index registers
 Special purpose register
 Flag registers
13
REGISTER ORGANIZATION
14
GENERAL PURPOSE REGISTER
 The are 4 general purpose register
 The are AX, BX, CX, DX
 Each can be split into two 8 bit
register
AL and AH, BL and BH, CL and CH
and DH and DL
 They can be used to holding data
variables and immediate results
15
GENERAL PURPOSE REGISTERS
16
SEGMENTATION
 The address bus width is 20 bit wide
 But all its registers are 16 bit width
 For these reason it partition its 1mb memory
into many 64kb memory segment and access
them individually
 8086 allow only 4 active segments at a time
 For the selection of the four active segments we
use segment register
 Code segment register
 Data segment registers
 Stack segment register
 Extra segment registers
17
POINTER AND INDEX REGISTERS
 They are also called offset registers
 To get a 20 bit address from 16 bit registers,
 Index register are associated with each
segments registers
 IPwith CS
 BP with DS
 SP with SS
 The DX and SI are used for
 As a general purpose register
 As offset register for some addressing modes
18
REGISTERS AND POINTERS
Segment register Pointer
CS (code segment) IP (instruction pointer)
DS (data segment) DI, SI
SS (Stack segment) SP (stack pointer)

BP (base pointer)
ES (Extra segment) DI
19
SEGMENT
REGISTER(CONTINUED)
 The code segment(CS) holds the
upper 16 bit address of the
instruction
 Stack segment(SS) holds the upper
16 bit address of the stack segment
 Data segment(DS) and extra
segment(ES) are used for holding
the upper 16 bit address of the
data segment
20
MEMORY SEGMENTATION
21
8086 REGISTER SETS
22
SPECIAL PURPOSE REGISTER
 Instruction pointer (IP)
Identifies the location of the next
instruction to be executed in the current
code segment
IP contains an offset value not the physical
address of the next instruction
Physical address = IP+CS*10h (code segment
register)
Every time an instruction word is fetched
from memory, the BIU updates the values in
IP (eg IP = IP+1) such that it points to the
next sequential instruction word in memory
23
FLAG REGISTERS
24
FLAG REGISTERS EXAMPLE
25
LAB FOR THE COURSE
 We will use emu8086 emulators
26
CONCLUSION
 Key concepts in today's class
 Pre-fetching
 Pipelining
 Advantage
 Disadvantage
 Functions performed by
 the BIU and
 EU ?
 Multiplexed of address and data bus
 The concept of segmention
27
NEXT CLASS
 Addressing mode

CS 477/677 - Lecture 1 28

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Department of Electrical and computer Engineering

College of Engineering and Technology

 Pre-fetch 6 byte of instruction in

CS (code segment) IP (instruction pointer)

DS (data segment) DI, SI

SS (Stack segment) SP (stack pointer)

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