Hardware Description Languages and Programmable Logic
Hardware Description Languages and Programmable Logic
Hardware Description Languages and Programmable Logic
(Assistant Lecturer)
E-mail: mwalongomarko@gmail.com
LECTURE 2:
VERILOG HARDWARE DESCRIPTION
LANGUAGE (HDL)
HARDWARE DESCRIPTION
LANGUAGES
HDLs provide a way to specify the design at a higher level
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BASIC CONCEPTS OF VERILOG
A HDL allows us to specify the components that
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BASIC CONCEPTS OF VERILOG
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ARCHITECTURAL FEATURES
TIMING AND
Behavioral
DATAFLOW
Verification
Data storage & movement
RTL
State machine specification
Verificatio
n
Breakdown into netlist of gates
Synthesis
of gates
Verification
Use netlist to create logic
Logic design network
Simulation
Tape ToBmy
BEHAVIORAL
A typical design hierarchy is portrayed in the
previous slide.
At the highest level is a behavioral description that
describes the system in terms of its architectural
features.
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Verilog HDL provides for descriptions of a digital
system at all of the levels listed.
Every level is related to every other level, and the
design philosophy is linked by the different types of
code.
Each level has its own coding style using certain sets
of commands and constructs.
The concept that links the various levels is that of a
module. A verilog module is the description of a unit
that performs some function.
Instantiations of simple modules are used to create
more complex modules.
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STRUCTURAL GATE-LEVEL MODELLING
Consider a 4-input AOI circuit. The logic is
constructed using primitive AND and NOR gates
that take the inputs a, b, c, d and produce an output
of f=NOT(a.b + c.d)
Keywords are boldface
variables.
STRUCTURAL GATE-LEVEL MODELLING
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IDENTIFIERS
Identifiers are names of modules, variables, and
other objects that we can reference in the design.
Identifiers consist of upper – and lowercase letters,
digits 0 through to 9, the underscore character (_),
and the dollar sign ($).
The first character must be a letter or a underscore
in normal usage. An identifier must be a single
group of character for example: input_control_A 20
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COMMENT LINE
In the statement
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PORTS
Ports are interface terminals that allow a module to
communicate with other modules. These correspond
to the input and output points on a library cell.
independent gates.
GATE DELAYS
The logic delay through a gate is sometimes modeled using a
single dalay time (propagation delay) from the input to the
output.
by a time scaling unit of s, ms, us, ns, ps or fs. The t_unit gives
the time scale, while t_precision give the resolution.
‘timescale 1ns/100ps
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If a gate instance is written as xor #(10)(out, A_0, A_1); The
GATE DELAYS
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The verilog listing in the previous slide simulates the module shown in
the figure of slide 33.
The first listing for module DelayEx has nothing new in it except for the
delay specifications.
format. 36
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THANK YOU!!!!!!!!!!
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