Aca Univ 2 Mark and 16 Mark
Aca Univ 2 Mark and 16 Mark
Aca Univ 2 Mark and 16 Mark
It is the part of the processor that is visible to the programmer. It serves as the boundary
between software and hardware.
4. What are the trend in technology? NOV/DEC 2016
It is the total amount of work done in a given time, such as megabytes per second for a
disk transfer.
6. Define latency(Response Time).
It is the time between the start and the completion of an event, such as milliseconds for a
disk access.
7. What is the maximum power a processor ever requires?
Modern processors can vary widely in power consumption with high peak currents, hence they
provide voltage indexing methods that allow the processor to slow down and regulate voltage
within a wider margin.
8. What is the sustained power consumption?
This metric is widely called Thermal Design Power(TDP), since it determines the cooling
requirement.
9. What is learning curve?
The cost of a manufactured computer component decreases over time even without major
improvements in the basic implementation technology. The underlying principle that drives costs
down in the learning curve, manufacturing costs decreases over time.
10. What is die?
Die is the square area of the wafer containing the integrated circuit.
11. How cost of die is calculated?
The cost of die is determined from cost of a wafer. The number of dies fit on a wafer and
the percentage of dies that work, ie., the yield of the die.
12. What is dependability? APR/MAY 2017
A memory that is smaller and faster than main memory and that is interposed between
CPU and main memory.
15. Define interrupt.
It is an event that causes the execution of one program to be suspended and another
program to be executed.
16. State Amdalh’s law.
It states that the performance improvement to be gained from using some faster mode of
execution is limited by the fraction of time the faster mode can be used.
17. What are the two-phase procedures in executing an instruction?
When operands are brought into the processor, they are stored in high-speed storage elements
called registers.
19. Explain the various classifications of parallel structures.
A group of lines that serves as a connecting path for several devices is called a bus.
21. What is the role of PC(Program Counter)?
The CPU contains a register called the program counter, which holds the address of
instruction to be executed.
22. What are the classes of computer?
A processor register is used to keep track of the address of the element of the stack that is
at the top at any given time.
24. Define memory access time.
The time required to access one word is called the memory access time.
25. Define latency.
The term memory latency is used to refer to the amount of time it takes to transfer a word
of data to or from the memory. It is used to denote the time it takes to transfer the first word of
data.
26. How to find the cost of an integrated circuit? NOV/DEC 2016
The technique used to overlap the execution of instructions and improve performance is
called ILP.
3. What are the approaches to exploit ILP?
Data dependences
Name dependences
Control dependences
6. What is loop level parallelism?
Pipeline CPI=Ideal pipeline CPI+ Structural Stalls+ data hazards stalls+ Control stalls.
8. Give the classification of data hazards.
The type of code scheduling which execute instructions before or after the branch
instruction which will not affect the program result is called speculation.
10. Define Dynamic scheduling.
It allows instructions to execute out of order when there are sufficient resources and no data
dependence.
13. Register renaming eliminates which types of hazards?
It is a small memory indexed by the lower portion of the address of the branch prediction.
It contains a bit that says whether the branch was recently taken or not.
17. What is two level predictors?
Branch predictors that use the behavior of other branches to make a prediction are called
correlating predictors or two level predictors.
18. What is loop unrolling?
It is a simple scheme for increasing the number of instructions relative to the branch and
overhead instructions.
19. What are the advantages of loop unrolling?
Very Long Instruction Word, Single instruction issue, but multiple operations per
instruction.
22. What is reorder buffer?
It holds the results of instructions that have finished execution but have not committed.
23. What is poison bit?
Poison bits are a set of status bits that are attached to the result registers written by the
speculated instruction when the instruction causes exceptions.
24. Mention the advantage of using tournament based predictors?
The advantage of tournament predictor is its ability to select the right predictor for right
branch.
25. Give an example of control dependence.
If p1 {s1;}
If p2 {s2;}
S1 is control dependent on p1,and s2 is control dependent on p2.
26. What are the types of multiple issue processors?
6. What are the compiler techniques for exposing ILP? Explain. NOV/DEC2016, APR/MAY
2017
7. Explain Dynamic Branch Prediction with neat diagram. APR/MAY 2017(CSE)
8. Explain Dynamic scheduling using Tomasulo’s algorithm. Explain how it is used to reduce
data hazards. NOV/DEC2016
9. Explain Speculation and its types./Briefly compare the hardware and software speculation.
APR/MAY 2017(ECE,CSE)
10. Write short note on ‘static scheduling’.
11. Explain the approaches of multi-threading. Explain how ILP is achieved using multithreading
with an example. NOV/DEC2016
12. What are the limitations of ILP? APR/MAY 2017
13. Explain the methods of exploiting ILP using VLIW processor. APR/MAY 2017(ECE,CSE)
UNIT –C(UNIT III) PART-A
1. What is data level parallelism?
Register-to-register model
Memory-memory vector processors
6. What are the types of data dependences in loop?
It occurs when two instructions use the same register or memory location called a name,
but there is no flow of data between the instructions associated with that name.
8. What is tree height reduction?
SIMD MIMD
Single Instruction Multiple Data Multiple Instruction Multiple Data
Architecture is simple Architecture is complex
Scalable size and performance Complex size and performance
11. Define dataflow models.
1. Instruction-level-parallelism
It is defined by the control and data dependence of programs. It deals with algorithm
function, optimization of compiler and programming styles.
15. What are the types of dataflow model?
In this, each processor assigns a task to perform and is responsible for all computations
related to those tasks. It is also known as reduction machines.
17. Define Vector processor.
Memory-to-memory model
Register-to-register model
19. What are the advantages of vector processor?
It is a single-chip processor used to manage and boost the performance of video and
graphics.
GPUs are used heavily in research and high-performance computing because of their
ability to run highly parallel code.
22. What are the reasons for finding the dependence?
Recurrences are expressions whose value on one iteration is given by a function that
depends on the previous iterations.
27. Define start up time.
Start up time for a load is the time to get the first word from the memory into a register.
28. Differentiate GPU and CPU. NOV/DEC 2016
29. What are the primary components of instruction set architecture of VMIPS?
30.What are the omissions in the SIMD extension instruction set? APR/MAY 2017
31.Describe the similarities and differences between multimedia SIMD computers and
GPU. APR/MAY 2017
3. Explain Vector Architecture with neat diagram./Explain Data level parallelism in Vector
architecture in detail. APR/MAY 2017
4. Explain GPU architecture with a neat sketch. APR/MAY 2017
5. Describe the concepts of Loop level parallelism with an example./Explain detecting and
enhancing loop level parallelism in detail. NOV/DEC2016
6. what are the mismatch occurred between software and hardware parallelism?
10. What are the two primary types of architectures for vector processors. Explain.
13. Discuss similarities and differences between vector architectures and GPUs. NOV/DEC2016
UNIT- IV PART A
1. What are multiprocessors? Mention the categories of multiprocessors?
These are multiple processors executing a single program and sharing the code and moat
of their address space
3. What is cache coherence problem?
Two different processors have two different values for the same location.
4. What are the protocols to maintain coherence?
Shared
Uncached
Exclusive
8. What are the uses of having a bit vector?
When a block is shared, the bit vector indicates whether the processor has the copy of the
block. When the block is in exclusive state,bit vector keep track of the owner of the block.
9. what is consistency? APR/MAY 2017(CSE)
It says in what order must a processor observe the data writes of another processor.
10. Mention the models that are used for consistency.
Sequential consistency
Relaxed consistency
11. What is multithreading?
It allows multiple threads to share the functional units of the single processor in an
overlapping fashion.
12. Define fine grained multithreading.
It switches between threads on each instruction, causing the execution of multiple threads
to be interleaved.
13. Define course grained multithreading.
It switches only on costly stalls. That it is much less likely to slow down the execution of
an individual thread.
14. What are the reasons to increase importance of multi processors?
Shared memory
Message passing multiprocessors
16. What do you understand by write update protocol?
The alternative to an invalidate protocol is to update all the cached copies of a data item
when that item is written. This type of protocol is called a write update or write broadcast
protocol.
17. List the two protocols used to track the status of the shared data block. How the status is
maintained in both the schemes?
Directory based - the sharing status of a block of physical memory is kept in just one
location, called the directory. Directory based coherence has slightly higher implementation
overhead than snooping, but it can scale to larger processor counts.
Snooping – Every cache that has a copy of the data from a block of physical memory
also has a copy of the sharing status of the block, but no centralized state is kept.
18. What is write invalidate and write update?
Write invalidate provide exclusive access to caches. It ensures that no other readable or
writable copies of an item exists when the write occurs.
Write update updates all cached copies of a data item when that item is written.
19. when do we say that a cache block is exclusive?
When exactly one processor has the copy of the cached block, and it has written the
block. The processor is called the owner of the block.
20. What is sequential consistency? NOV/DEC 2016
It requires that the result of any execution be the same, as if the memory accesses
executed by each processor were kept in order.
21. What is relaxed consistency model?
It allows reads and writes to be executed out of order. The three sets of ordering are
W R ordering, WW ordering, RW ordering and RR ordering.
22. What is meant by cache coherence problem?
The two different processors can have two different values for the same location.This
difficulty is referred to as cache coherence problem.
23. What do you understand by write update protocol?
The alternative to an invalidate protocol is to update all the cached copies of a data item
when that item is written. This type of protocol is called a write update or write broadcast
protocol.
24. Differentiate between write invalidate and write update
The data for a write miss can always be retrieved from the memory.
26. List the methods for providing synchronization in threads. NOV/DEC 2016
UNIT- IV PART B
1. Explain distributed memory architecture with neat diagram. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
2. Explain the architecture of symmetric shared memory with a neat sketch.
6. Explain the features of SMT & CMP processors with a neat sketch. APR/MAY 2017(CSE)
13. Explain about synchronization techniques used in multiprocessor system. APR/MAY 2017
UNIT-V PART-A
1. What is memory?
Memory is a device used to store and data and instructions required for any operation.
2. What is bandwidth?
The maximum amount of information that can be transferred to or from the memory per
unit time is called bandwidth.
3. Define cache.
It’s a small fast intermediate memory between the processor and the main memory.
4. Give the mapping techniques of cache.
Direct mapping
Fully associative
Set associative
5. What is write stall?
When the processor must wait for writes to complete during write through, the processor
caches is said to write stall.
6. Define mapping functions.
The correspondence of memory blocks in cache with the memory blocks in the main
memory is called as mapping functions.
7. What is address translation?
The average time to move a arm to the desired track is called seek time.
9. Define rotational latency.
The time taken to move the read writes head to a particular sector.
10. Define page fault.
If the processor access for the particular page in main memory and if the page is not
present there then it is known as page fault.
11. Define cache hit.
When the CPU refers to memory and finds a required word in cache it is called as cache
hit.
12. Define hit ratio.
The ratio of the number of hits divided by the total CPU references to memory is the hit
ratio.
13. Define miss.
When the CPU refers to memory and if the required word is not found in cache, is called
as miss.
14. Write a formula for average memory access time.
Average memory access time = hit time + miss rate × miss penalty
15. List the method to improve the cache performance.
It is used to all the tracks under the arms at a given points on all surfaces.
17. What is transfer time?
It is the time it takes to transfer a block of bits, typically a sector under read/write head
18. What is called pages?
The address pages is usually broken into fixed-size blocks, called pages. each page
resides either in main memory or on disk.
19. What are the categories of cache miss?
RAID is Redundant Array of Independent Disks. It is a way of storing the same data in
different places on multiple hard disks.
21. What is write back?
If the write is deferred until the cache line is flushed from the cache, is called as write
back.
22. Compare software and hardware RAID.
Recently referenced items are likely to be referenced again in the near future. This is
often caused by special program constructs such as iterative loops, process stacks, temporary
variables or subroutines
24. Define spatial locality. APR/MAY 2017(CSE)
It refers to the tendency for a process to access items whose addresses are near one
another.
25. what is miss penalty?
The number of stall cycles depends on both the number of misses and the cost per miss,
which is called the miss penalty.
26. What is memory stall cycles?
The number of cycles during which the CPU is stalled waiting for a memory access is
called memory stall cycles.
27. What is synchronous bus?
It includes a clock in the control lines and a fixed protocol for sending address and data
relative to the clock.
28. Explain the difference between latency and throughput.
Latency is defined as the time required processing a single instruction, while throughput
is defined as the number of instructions processed per second.
29. What are the techniques to reduce hit time?
Eight way: conflict misses due to going from fully associative to eight way associative
Four way: conflict misses due to going from eight way associative to four way
Associative
Two way: conflict misses due to going from four way associative to two way associative
One way: conflict misses due to going from two way associative to one way associative
31. List the six basic optimizations techniques of cache. NOV/DEC 2016
8. What is RAID. Explain its levels with neat sketch. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
9. Write short note on
a) Reliability
b)Availability
c)Dependability
10. Mention performance measures of I/O system. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
11. What are the techniques are used to reduce miss rate? Explain.
12. Define Virtual memory. Explain the techniques for fast address translation.
15. Explain the categories of misses and how will you reduce cache miss rate. NOV/DEC2016
~~~~~~~~~~~~~~~~~~~~~