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Modern electronic packaging technology

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M. G. BEVAN AND B. M. ROMENESKO

Modern Electronic Packaging Technology

Matthew G. Bevan and Bruce M. Romenesko

A view of modern electronic packaging technology is presented along with its

applications at APL. Although not always distinct, electronic packaging may be
separated into three levels: component, board, and system. The manufacturing
technologies and designs may vary at each level, but they all must provide electrical
interconnection, thermal management, and mechanical and environmental protection.
Each packaging level reflects a trade-off among many interrelated factors including
design requirements, economics, and manufacturing infrastructure.
(Keywords: Electronic components, Electronic packaging, Packaging design, Packaging
levels.)

INTRODUCTION
Electronic packaging serves a fourfold function for Published information about electronic packaging
the electronic circuit by providing it with power and technology is in abundance today. This article will
signal interconnection, a path to dissipate heat, me- touch on the critical aspects of packaging technology
chanical support, and a protected environment that and how they are applied at APL. For additional infor-
prevents contamination, mechanical damage, and elec- mation, the reader may consult the selected bibliogra-
tromagnetic interference. In some applications (e.g., phy at the end of this article, which lists several refereed
biomedical), the packaging also protects the environ- journals, conference proceedings, and books that track
ment from contamination by the electronics. progress in the packaging field.
Proper packaging design requires identification of
the critical issues involved such as performance needs,
the application environment, manufacturing capabili- PACKAGING DESIGN
ties, system heritage, testing, reliability, cost, and Over time, the trade-off in requirements has divided
schedule. Electronic packaging technology uses a electronic packaging into three levels (Fig. 1): device
variety of fabrication techniques such as welding, packaging, board packaging, and system packaging.
electroplating, and injection molding to accomplish its Although separation into these levels is not absolute,
purposes. they reflect a common method used to organize the

22 JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999)

 MODERN ELECTRONIC PACKAGING TECHNOLOGY

placement, material choices, and

Subsystem space allocation.
chassis Incorporation of off-the-shelf
assemblies into the product drives
many packaging decisions. Such
Single-chip
assemblies perform crucial func-
package tions and have their own electrical
and mechanical interfaces. There
may be many electronic, optical,
and mechanical subassemblies to be
Die incorporated into an assembly, for
example, power supplies, charge-
MCM
coupled device cameras, disk
drives, card guides, card cages, and
connectors. For optimum perfor-
mance, these subassemblies usually
COB require exacting design consider-
ations such as special mounting
brackets and connectors, heat sink-
ing, and environmental protection.
Although these design factors
Figure 1. Three levels of packaging: the device is packaged into a component, the
component is mounted on the board, and the board is installed into the subsystem chassis
are critical in the prototype and
(MCM = multichip module, COB = chip-on-board). one-of-a-kind hardware that APL
designs and builds, commercial and
military electronics may have addi-
electronic circuitry and categorize electronic packaging tional life cycle and consumer appeal issues. Life cycle
requirements. Each level of packaging provides similar issues such as maintainability and testability must be
functions but has a distinct purpose and design. accommodated. Ergonomics and visual appeal are high
Device packaging protects the integrated circuit priorities in many consumer electronic products. Final-
from corrosion and dissipates heat, creating a compo- ly, and usually most importantly, the packaging design
nent with an electrical interface and mechanical sup- must fall within the cost and schedule constraints of the
port for installation and testing. The printed wiring product.
board or substrate provides support and interconnec-
tion of the device packages to create electronic sub-
functions suitable for higher-level testing. Box-level Packaging Reliability
packaging allows for electronic interconnection be- Reliable packaging begins in the design stage. At
tween the circuit substrates, and performs housing and this point, the packaging engineer must consider the
interfacing (such as connectors or keyboards) to the potential for thermal, mechanical, and corrosion prob-
outside world. Partitioning of the electronic system is lems and determine the best method to minimize their
a process that breaks down the complete electronic effects.
circuit into these different levels. The breakdown con- Heat is a by-product of the circuit’s function that
siders many factors. This process requires an under- raises component temperature and can reduce its reli-
standing of the circuit and its subfunctions, component ability. This temperature increase is an internally gen-
and assembly availability, application requirements, as erated stress that must be accounted for in the package
well as development and testing needs. design. Below some threshold, elevated junction tem-
Meeting performance requirements is foremost in perature has little effect on the life of a part, but above
electronic packaging. Factors such as signal speed, noise that threshold, component life shortens exponentially
sensitivity, and electromagnetic interference often dic- with increasing temperature. Thresholds range from
tate the approach to packaging. Signal speed may re- 100 to 150°C,2 depending on the expected product
quire substrates with a low dielectric constant or im- lifetime, circuit design, and materials. Hence, the pack-
pedance matching. Noisy circuits and circuits that age’s ability to dissipate the device’s heat closely cor-
generate electromagnetic interference may hamper the relates to its reliability. Proper thermal package design
proper functioning of adjacent circuits and may need ensures that the heat dissipation path maintains the
to be separated from other sensitive circuits by shield- junction temperature below the threshold value. High-
ing the device or filtering the power and signal lines.1 power devices may require special packaging design and
These design considerations often dictate component materials to minimize the junction temperature.

JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 23

M. G. BEVAN AND B. M. ROMENESKO

Although most circuit boards have sufficient free air increases the elastic modulus of the polymeric material
convection to safely dissipate heat from the device by several orders of magnitude, making the polymer
package, some do not because of high component much more stiff and brittle. Although going below the
densities or high heat generation from power transis- Tg does not damage the material, the change in mod-
tors, or because they operate in the vacuum of space. ulus, coupled with its dimensional change, can cause
In these situations, special features must be incorporat- unexpected fracture and fatigue. Concern for this fail-
ed to increase heat removal from the component.3 As ure mode has driven the APL Space Department
with personal computers, fans work well in many ter- to switch conformal coatings used on printed circuit
restrial environments, increasing heat transfer approx- boards from Solithane 113/300 (Tg = –10°C) to Ura-
imately an order of magnitude over free convection.4 lane 5750 (Tg = –65°C) (G. Arakaki, personal commu-
In a vacuum, however, it may be necessary to improve nication, Mar 1990; also see Ref. 6).
the thermal path between the device package and sub- In oceanic environments, exposure to corrosion can
strate. This may be accomplished by filling the gaps severely affect the performance and reliability of a
between them with a thermally conductive material. circuit. Moisture, in the form of saltwater or condens-
Thermal resistance may be lowered across the substrate ing humidity, promotes corrosion of electronic circuits.
by bonding a metal heat spreader to it to improve heat Corrosion products may form between adjacent electri-
flow to the surrounding box. cal conductors, creating an electrical short between
In addition to component temperature, the mechan- them and interfering with overall circuit performance.
ical environment may reduce the reliability of the elec- In addition, corrosion may dissolve conductors, thereby
tronic circuit. Specifically, factors such as vibration and severing the electrical path. The design engineer may
shock, along with temperature changes of the system, incorporate design features to slow or prevent corro-
induce forces that can break components and cause sion, such as conformal coating and encapsulation of
fatigue failure of leads or solder joints. By modeling, the the circuit boards.
packaging engineer can identify these potential prob-
lems early in the design stage and implement design
modifications to mitigate these forces. System Partitioning and Modeling
Over the circuit’s lifetime, the thermal stresses on After defining the top-level circuit, its environmen-
the assembly are frequently more destructive than those tal requirements, and its physical constraints, the sys-
created by shock and vibration. In the assembly of tem is partitioned into subsystems and components.
electronic packages and circuit substrates, a variety of Then, packaging engineers develop detailed designs
materials are bonded together with adhesives or solders. that satisfy the requirements of the subsystems. At this
Because of the dissimilar thermal expansion of these point modeling is often used to predict the thermal and
materials, temperature changes generate forces at bond mechanical behavior of the system so that shortcom-
interfaces. For stiff materials, these forces may be suf- ings in the packaging designs can be identified before
ficiently large to cause fracture or fatigue failure. Given fabrication begins.
the prevalence of problems caused by temperature Partitioning breaks down a system into logical ele-
cycling in the aerospace industry, spacecraft environ- ments, usually organized by function, testing needs, and
mental stress screening performed by APL includes physical size. Additional design considerations that
both temperature cycling and thermal shock tests to affect partitioning may include standard circuit board
screen for potential problems. sizes, thermal management, and available space. Parti-
Prevention of temperature cycling damage usually tioning is frequently organized by electrical function to
requires attention to design or material selection. One aid in testability, such as having one circuit card ded-
common solution is to place an intermediate soft or icated to power supply or to data communications.
spring-like material between the two high-modulus Careful partitioning of the electronic circuit simplifies
materials. The intermediate material absorbs the strain testing significantly.
differences between the adjacent materials, reducing In early Terrier missiles, the electronic components
the overall stress. An example of this is the Tessera were hand wired, part by part, to the airframe.7,8 As a
chip-scale package (CSP),5 where silicone rubber is result, the assembled missiles frequently failed accep-
used between the low-expansion silicon device and the tance tests because of a multitude of problems. The lack
higher-expansion flex circuit. Alternative solutions of functional subdivision made testing, troubleshoot-
include replacing high-modulus materials with low- ing, and repair difficult and time-consuming. Improved
modulus materials or improving the match in the co- missile designs partitioned the circuits into subsystems
efficients of thermal expansion. (e.g., attitude control, telemetry, fusing), making the
Temperature-induced damage may be particularly missile easier to assemble, test, and repair. This same
severe when using polymers near their glass transition functional division concept applies to the different
temperature, Tg. Cooling a polymer below this level levels of packaging.

24 JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999)

 MODERN ELECTRONIC PACKAGING TECHNOLOGY

Other issues besides testing drive (a) Primary side Secondary side

the partitioning decisions. Parti-

tioning usually accommodates the
normal manufacturing sequence to
minimize handling and cross-con-
tamination. Systems may require
additional volume and features to
allow for repair, or they may be
partitioned to minimize the amount
of circuitry in an adverse environ-
ment. For example, on spacecraft,
even though the sensors are ex-
posed to the space environment,
the boxes containing most of the
support electronics are placed un-
der thermal blankets to protect
them from the temperature ex-
tremes and temperature cycling en-
countered in space.
Analytical modeling is an essen-
tial tool in the partitioning and de-
velopment of reliable electronic
packaging designs. Modeling offers
significant cost and schedule sav-
ings for complex systems, particu-
larly those incorporating expensive (b) Downconverter
(400 mW)
and long lead-time subassemblies.
250-mW T08
Using specialized software, electri- can component Temperature
cal modeling can be performed to rise (°C)
37
simulate circuit performance. The Upconverter
34
(800 mW)
mechanical and thermal behavior 75-mW T08
32
29
of the system can be modeled using can components 26
finite element methods9 during 24
21
power cycling, temperature cycl- 18
ing, and shock and vibration test- 16
13
ing. By doing so, problems can be 10
identified and fixed, with minimal 8
5
impact on cost and schedule, before 2
any hardware is fabricated.
Figure 2 shows how modeling (c)
can predict problems before assem-
bly. Figure 2a is a schematic illustra-
tion of the full signal translator
circuit board. Figures 2b and c illus-
trate the results of thermal and me-
chanical modeling. Thermal mod-
eling predicts the temperature
distribution across the board. Figure
2b shows that the ambient temper-
ature must be kept at least 38°C Maximum deflection
below the critical junction temper-
ature of the upconverter. The me-
chanical analysis in Fig. 2c shows Figure 2. Modeling is used to predict problems before assembly. (a) Part locations on the
the deflection of the assembled front and back of a full signal translator (FST) circuit. (b) Thermal model of the FST showing
predicted component and substrate temperature (and its distribution over ambient condi-
printed wiring board under a sinu- tions). (c) Mechanical modeling showing first-mode deflection of the FST board in vibration;
soidal vibration. The software not the mass of the upconverter causes most of the deflection.

JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 25

M. G. BEVAN AND B. M. ROMENESKO

only predicts the maximum deflection, it also predicts these reasons devices are usually packaged before test-
the distribution of the deflection across the board, ac- ing and further assembly.
counting for variations in mass and specific locations The design of the device packages is driven by many
of mounting points. By knowing the deflection loca- factors, including the number of leads and their routing
tions and magnitudes at the design stage, additional on the substrate as well as the ability to dissipate the
stiffeners and mounting points may be incorporated in heat generated by the device. The external lead geom-
the design before the hardware is built. etry must meet the customer’s circuit board design con-
Once the hardware is built, the thermal model is straints, assembly needs, and cost requirements. To con-
verified by measuring the temperature at critical loca- serve the space on a circuit board, customers frequently
tions. Since measuring deflection during vibration is want the device in the smallest package possible.
somewhat difficult, strain or acceleration measure- Smaller packages permit significant system miniaturiza-
ments obtained via gauges and accelerometers, respec- tion. Figure 4 shows how smaller packages may have the
tively, may be used to validate the mechanical behavior same number of leads as larger packages but cover a
of a model. considerably smaller substrate area. However, miniatur-
ization of packages frequently results in increased costs
DEVICE PACKAGING of assembly.
The first or lowest level of packaging is semiconduc- The redesign of the Glacier spaceborne imager built
tor device packaging. Not long ago, the selection of by the APL Space Department exemplifies how chang-
package styles was limited. The dual-inline package ing component packaging can reduce overall system
(DIP) dominated the semiconductor market and rep- size. The imager was an existing circuit design that was
resented the majority of electronic packages sold. To- repackaged using several new packaging technologies
day, with the drive toward miniaturization, combined (see the article by Le et al., this issue). By stacking
with the lack of a clearly superior miniature package, dynamic random-access memory vertically, about a 5:1
many distinct package styles are available (Fig. 3), reduction was realized in the number of packages, with
ranging from traditional DIP to chip-on-board (COB). a corresponding reduction in substrate area. Attaching
They also range in price and area of substrate required bare, unpackaged devices directly to the substrate in-
for installation, each reflecting a different testing, as- stead of packaged devices contributed to further min-
sembly, and performance optimum. iaturization. However, these savings came at a price.
The primary motives for packaging the device before Stacked memory chips are more expensive than sepa-
assembly onto a circuit board are to allow for complete rately packaged devices. Also, attaching unpackaged
testing and to protect the device from contamination. devices introduces a host of potential problems: un-
Without packaging, testing of bare devices is expensive packaged and incompletely tested parts create an in-
and difficult because of the tiny dimensions involved. creased amount of rework, increased rework difficulty,
When packaged, a device has far less stringent handling additional costs associated with encapsulating the de-
requirements than a bare device. Bare silicon devices vice after attachment, and reliability unknowns found
must be handled cautiously in a clean-room environ- with any new assembly method.10
ment. Soldering and normal handling during assembly
leave contamination that often causes corrosive failure Device Packaging Processes
of unprotected devices. Improper handling easily A variety of processes are used in device packaging.
damages the tiny wire interconnections on devices. For These processes create a package that shields the die
from contamination and damage
while electrically connecting it
to the exterior. One of the most
critical processes is the electrical
interconnection of the device to
the leads. This can be achieved
through, for example, wire bond-
ing, tape-automated bonding
(TAB), and flip-chip soldering.11
Historically, wire bonding has been
the dominant method of intercon-
0 1 2 3 4 5 nection. When a wire bond is
Centimeters made, the wire bonding machine
welds one end of the wire to the
Figure 3. Some components available today are (clockwise from lower left) a 44-pin J-
leaded plastic quad flatpack (PQFP), 20-pin thin small-outline package, 84-pin J-leaded device and the other end to the
PQFP, 208-pin QFP, 100-pin QFP, and 40-pin dual-inline package. substrate or lead frame. Wire bonds

26 JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999)

 MODERN ELECTRONIC PACKAGING TECHNOLOGY

$0.001 per connection for wire

bonding.12
The TAB method is an alterna-
tive to wire bonding and flip-chip
bonding. It incorporates the bond-
ing region with the lead frame fan-
out. A TAB structure typically be-
gins as a thin laminate of copper on
a polyimide film carrier. The con-
ductors are etched out of the copper
to form the electrical interconnec-
tion between the chip and the out-
side. The polyimide holds the cop-
per conductors in place to facilitate
rapid assembly. TAB technology
uses several metallurgical coatings
for conductors and bonding areas.
Methods of connecting the TAB to
the chip include thermocompres-
sion, thermosonic and ultrasonic
Figure 4. Plot showing the amount of substrate area required per lead and how this ratio bonding, and soldering. Joints may
varies with package style and total number of leads on the package. (DIP = dual-inline
package, PLCC = plastic-leaded chip carrier, TSOP = thin small-outline package, QFP = be bonded one at a time or si-
quad flatpack, BGA = gall-grid array, PBGA = plastic BGA.) multaneously. The process is rapid
and has found niches in certain
are made using thin gold or aluminum-alloy wire, typ- markets. In low-volume markets (e.g., high-performance
ically with a diameter of 25 mm (0.001 in.). Wire bonds military electronics), TAB offers a highly reliable, high-
are short, in the range of 1 to 3 mm (0.05–0.15 in.). performance interconnect method with a minimum of
Because they are so short and fragile, they impose ad- inductance and impedance. In high-volume markets,
ditional packaging requirements. The frail wire bonds TAB offers a low-profile way to assemble circuits for
must be protected from damage and contamination, applications such as digital watches and cameras.
either by encasement in a rigid package or by molding Wire bonding, flip-chip soldering, and TAB may
in plastic. require additional features for mechanical and thermal
In the 1960s, IBM developed an alternative to wire interconnection. In wire bonding, the back of the
bonding, now called flip-chip technology, which uses device must be attached to a substrate using an adhe-
a solder joint to form an electrical, thermal, and sive, gold-silicon eutectic solder or a glass compound.
mechanical connection to the substrate. The flip The adhesive is often filled with silver or gold powder,
chip process produces higher yields and more rapid making it electrically conductive and enhancing ther-
throughput than wire bonding. Additionally, it re- mal conductivity. Because of the large surface area in-
quires less space on a substrate than wire bonding and volved, device attachment provides a good thermal
permits rework. As expected, these advantages also connection and high mechanical strength.
have their cost. Flip-chip technology is more challeng- Flip-chip technology does not require additional me-
ing to implement for much of the electronics fabrica- chanical attachment because the solder joints provide
tion industry. The process requires special metalliza- sufficient support to withstand shock and vibration
tion during wafer fabrication. A barrier layer and a forces. The flip-chip solder joints, by themselves, can
solderable top-layer metallization must be applied over dissipate considerable device heat. If further measures
the aluminum bond pads to provide a solderable sur- are needed to remove heat, two options are available.
face and prevent aluminum dissolution in the solder. In the most demanding applications, heat may be re-
The barrier layer must be compatible with a solderable moved from the back side of the flip chip through
top layer, protect the surface of the semiconductor conduction by using a small block of water-cooled cop-
device from contamination, and prevent undesirable per such as that used in the IBM thermal control
metallurgical reactions between the solderable layer module.13 The second option is to fill the gap between
and the device metallization. Flip-chip technology the flip chip and the substrate with an encapsulant,
also requires a nonstandard substrate and processing called “underfill,” to increase thermal conductivity.
of the substrate to reduce the size of the pads, vias, This underfill also provides environmental protection
and traces. For these reasons, the cost of a flip chip to the device circuitry and improves the thermal fatigue
is about $0.05 per connection versus less than resistance of the solder joints.

JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 27

M. G. BEVAN AND B. M. ROMENESKO

Wire bonded, soldered, and TAB-mounted devices reduced significantly with only a slight compromise of
all require environmental protection from handling, component density.
contamination, and corrosion. This protection takes The number of leaded surface-mount package styles
one of several forms. Devices may be sealed in the has proliferated without a single unifying standard.
cavity of a ceramic or metal hermetic package whose Several package design standards have been developed,
walls are impervious to humidity and contamination, each defining different package geometries and differ-
encapsulated in epoxy or silicone, or coated with inor- ent lead layouts. Each package style has unique benefits
ganic materials such as silicon nitride. A common en- and constraints. As the lead size becomes smaller and
capsulant is a filled epoxy that has been injection the number of leads increases, the difficulty of handling
molded around the device and its lead frame. This and installation increases. Some package styles are
material is used extensively for commercial compo- better suited for heat dissipation than others, a factor
nents. As an alternative to injection-molded materials, vital in space and temperature-critical applications.
a castable encapsulant may be applied, either as an The development of area array surface-mounted
underfill for flip-chip assembly or mounded as a “glob- packages (Fig. 5) offers both the benefit of increased
top” over a wire bonded device to protect the wires. lead densities and a more forgiving manufacturing pro-
cess. These packages distribute the solder joints, which
number from 48 to over 1000,14 across the bottom
Component Package Styles surface of the package instead of along the edges. This
One of the oldest and most common component distribution allows for larger solder joints and an in-
packages is the DIP noted previously, which is fabricat- creased distance between them, thereby improving
ed in three basic configurations: molded plastic, ceram- solder joint manufacturing yields and reliability. These
ic, and side-brazed. The plastic injection-molded solder joints provide both electrical connection and
DIP dominates cost-sensitive and noncritical applica- mechanical support for the component.
tions, whereas the ceramic and side-brazed packages, An early implementation of area array interconnects
with their hermetic seals, are used in high-cost, high- was the pin-grid arrays found on microprocessors in the
reliability applications found in military, space, and early 1990s. Today, two leadless types of area array
demanding commercial electronic systems. The DIP packages are being implemented, the ball-grid array
has two rows of leads separated by 0.3, 0.4, or 0.5 in., (BGA) and the chip-scale package (CSP). The distinc-
with the individual leads spaced 0.1 in. apart. The size tion between these packages is more an issue of scale
of the DIP is based not so much on the device size but than design. The BGA is larger and is built on a printed
rather on the area required by the spacing of the leads. circuit board–like substrate. It has solder balls on the
The lead layout of the DIP consumes the greatest area bottom in a grid with nominally 1- to 1.5-mm (0.04-
per lead of any device packaging method. to 0.12-in.) spacings. The CSPs are approximately 20%
The DIP package is being replaced with surface- larger than the semiconductor devices they contain,
mounted packages for a number of reasons. With de- having correspondingly smaller solder balls and grid
vices becoming faster and more complex, the length of spacings ranging from 0.5 mm (0.020 in.) to less than
the component leads and substrate traces must be re- 0.1 mm (0.004 in.). To enhance solder joint fatigue life,
duced as the number of leads is increased. The in- the solder joints on CSPs are typically encapsulated
creased number of components parallels the need to with limited-expansion epoxy.
reduce the overall size of the system. Surface-mounted These package styles are so efficient in their use
packages satisfy these requirements in a variety of of substrate space that, to ease routing and reduce
shapes and sizes (Fig. 3). These packages can be grouped substrate costs, only the outer two or three rings of
into two general styles, leaded and area array. Figure 4 solder joints are often present or electrically active.
shows how surface-mounted packages, particularly area Among the most significant factors that limit area array
arrays, offer significant area savings when they replace packages are their sparse commercial availability and
DIPs. Area arrays are a class of packages that distribute the inability to visually examine the finished solder
leads on a grid pattern over the package bottom rather joints. This inability is a process quality issue that gives
than only around its periphery; this method makes high many companies problems. Nondestructive examina-
lead count devices much more practical. tion of the solder joints requires an X-ray machine
The area savings of surface-mounted components capability that few electronic assembly companies pos-
are often so great that substrate routing difficulties sess. Transmission X-ray analysis detects many types of
place more constraints on component density than the solder joint defects. A detailed, nondestructive analysis
component size. A substrate designed to fully exploit of solder joint shape requires X-ray laminography, but
the potential component density may have many layers most companies are satisfied with nondestructive
and may be costly. By limiting the board thickness transmission X-ray analysis combined with sampling
to four layers of metallization, the board cost can be methods using destructive analysis techniques. With

28 JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999)

 MODERN ELECTRONIC PACKAGING TECHNOLOGY

(a)
establish reliability limits for high-
reliability applications.16 Today, the
use of BGA and CSP packages in
these applications is limited to sit-
uations where no other traditional
package can meet the requirements.

MULTICHIP MODULE
0 1 2 3 4 5 PACKAGING
Centimeters Sometimes it is advantageous to
package several devices in one
(b) package, forming a multichip mod-
ule (MCM). By combining individ-
ual devices and components into a
single package, significant minia-
turization is achieved over individ-
ually packaged devices mounted on
a substrate. In doing so, multichip
packaging muddles the distinction
between device packaging and cir-
cuit boards.
0 1 2 3
The combination of Level 1 and
Centimeters
2 packaging into an MCM offers a
significant advantage of low-vol-
(c) Solder balls, ume, high-density packaging com-
Flexible circuit tape Soldermask or
eutectic or solid core
with or without adhesive coverlayer
monly found in the aerospace and
(solid core shown)
(shown with adhesive) military markets. In low volume, an
Low-modulus
Gold-plated encapsulant MCM is an economical alternative
bond ribbon to a custom-designed integrated cir-
cuit, since much of the miniaturiza-
tion is achieved without the high
Elastomer pad initial cost of integrated circuit de-
sign. Many highly integrated devic-
es began as an MCM before subse-
Silicon die
quent production volume justified a
commitment to redesign as a single
silicon circuit. The disadvantages to
MCM technology over individually
Figure 5. Several views and implementations of array packages. (a) Top and bottom views
of a ball-grid array. (b) Bottom view of chip-scale packages (CSPs). (c) Cross-sectional packaged devices are significantly
view of a CSP. (Photograph courtesy of Tessera, Inc.) higher costs of the assembly and
decreased yield caused by using in-
the high yields possible with BGAs and CSPs, completely tested silicon die. Verification of device
many companies choose to forgo the X-ray inspection performance without packaging (i.e., the “known-
of solder joints and, instead, monitor the assembly pro- good-die” problem) has received considerable attention
cess closely. in the electronics industry, but little progress has been
Heat dissipation is usually not a problem for BGAs. made in the ability to do so. The critical issues are cost
For example, Olin has developed a high-performance and system yield, for without the high probability of a
256-ball BGA (27 3 27 mm) package that, when dis- working device, assembly yields are low (Fig. 6), and
sipating 1 W, can be as little as 12.5°C over ambient the test and rework costs increase exponentially.
temperatures with natural convection.15 Multichip packaging substrates range widely in
The reliability of these new surface-mounted area cost and interconnect density. Those MCMs with
arrays has been tested and found to be satisfactory for printed circuit board substrates have the lowest cost
commercial applications; however, their history of use and lowest interconnect density; those with single-
is short—too short to build confidence for space and crystal silicon substrates have the highest cost and
military applications. Efforts are now under way to highest interconnect density. Alumina and other

JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 29

M. G. BEVAN AND B. M. ROMENESKO

In designing a circuit substrate,

Percent the shock and vibration environ-
90–100 ment of the application must be
100
80–90 accommodated. Because compo-
70–80 nents are small, damage from shock
90 60–70 and vibration forces usually is not
80 50–60
an issue in device packaging. With
system functioning (%)

70 40–50
larger substrates like circuit boards,
Probability of

30–40
60
20–30
however, both mass and moment
50
0 10–20
increase, thereby increasing the po-
40 0–10 tential for damage. As noted earli-
0.4
30 er, typical methods to reduce shock
0.8 and vibration damage include the
20 Defect rate
1.2 of parts (%) addition of stiffeners and extra
10
mounting points. Reducing the dis-
0 1.6
1
tance between mounting points
20 40 60 2.0 mitigates the deflection from the
80
Number of parts in system 100 shock and vibration and changes
Figure 6. Plot of system yields (probability of functioning) with the reliability of the the fundamental resonant frequen-
component and the number of parts in the system. cy. Adding stiffeners to the sub-
strate may also reduce the deflec-
ceramic substrate technologies represent cost/density/ tion and stresses on the components.
performance trade-offs between these two extremes. Conformal coatings are applied to assembled circuit
Traditionally, suppliers of MCMs for military and substrates for many purposes. If the circuit substrate is
aerospace applications place them in hermetic packages exposed to moisture and ionic contamination, it may
constructed of ceramic, glass, and metal. Hermetic require conformal coating to insulate the surface. Some
packages provide a barrier to moisture and relatively circuits on the Tomahawk cruise missile are immersed
constant mechanical and electrical properties over a in fuel, requiring conformal coatings that not only pro-
wide temperature range. A less expensive alternative is tect the circuit from corrosion but are also stable in fuel.
encapsulation of MCM circuits in an epoxy or silicone The Space Department uses conformal coatings not so
polymer. These encapsulants slow moisture ingress much to prevent corrosion but to dampen shock and
and mitigate corrosion, meeting the reliability require- vibration as well as to prevent stray metal contamina-
ments of many applications. Although their protection tion from shorting the circuit. Conformal coatings may
is not as assured, encapsulation is sufficient for many have one of several polymer chemistries.11 Polyure-
environments. thane, silicone, and Parylene conformal coatings are
Multichip packaging has a long history of use at APL commonly applied to circuit boards assembled at APL.
in satellites and special-purpose circuits (Fig. 7).17 The
Laboratory has fabricated MCMs on several types of
substrates including silicon wafer, low-temperature co-
fired ceramic, and thick film ceramic. These MCMs are
typically mounted in hermetic packages that are sealed
by soldering or welding. (See the article by Blum et al.,
this issue, for further details on MCM development at
APL.)

THE CIRCUIT SUBSTRATE

The purpose of the circuit substrate is to provide
a mounting surface and electrical interconnection
for the components. For most electronics, the circuit
substrate turns off-the-shelf components into a custom,
application-specific circuit. Considerations in the
choice of a substrate and its design include such assem-
bly processes and performance issues as signal delay and
Figure 7. An APL-designed and -fabricated static random-access
capacitance. The circuit substrate should allow for memory module using MCM technology. Module area is 3.5 3
testing and repair before integration into the next level. 4.1 cm.

30 JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999)

 MODERN ELECTRONIC PACKAGING TECHNOLOGY

A printed circuit board is normally fabricated as an or in areas with odd shapes. It also permits the circuit
epoxy or polyimide fiberglass composite structure. It to be assembled and tested flat, then folded into the
contains layers of copper traces on the surface and available space. Many consumer electronic products
within the structure that are connected by metallized such as cameras and watches contain such flexible sub-
vias. Components are soldered to the surface and in strates.
through-holes. The materials and processes used at Rigid-flex boards combine the advantages of both
APL to fabricate substrates were developed to maxi- flexible and rigid substrates. Such composite structures
mize electrical performance within cost and durability use flexible segments to connect rigid portions of the
constraints. For example, the coefficients of in-plane circuit board (Fig. 8). One common application of
thermal expansion of the composite and the copper rigid-flex boards is for motherboards. Before rigid-flex
traces are similar, minimizing substrate warpage during technology, the motherboard was connected to the
soldering and temperature cycling. external connectors using up to hundreds of discrete
Most vias extend through the entire thickness of the wires. This manual wiring process was time-consuming
board, connecting any of the inner layers of the board and error prone. By substituting a segment of flex
to the surface. This configuration limits the routing of substrate for the discrete wires, the wiring process is
traces to the space between the vias. Blind and buried reduced to soldering the connector pins onto a board,
vias (i.e., vias that do not extend through the board) thereby eliminating problematic hand wiring.
avoid this constraint but significantly increase the price
of the board. A blind via extends from the surface of
the substrate to a dead end at an inner layer; a buried
via begins and ends on inner layers of the substrate. CHASSIS-LEVEL PACKAGING
These special types of vias ease routing by limiting via Chassis-level packaging connects the circuit boards
length, allowing a trace to be routed above or below and mounts them into a chassis, forming a system or
the area that would otherwise be occupied by the via. subsystem. For many systems (e.g., personal comput-
Although boards with these special types of vias are ers), this is the level of packaging seen by the user. In
costly, they may still be more economical than the use satellites, this chassis-level package is connected to a
of silicon or ceramic alternatives. structural frame and electrically connected to other
Several variations to the traditional board offer al- chassis having different functions. The design phase of
ternative packaging options. New advances in ceramic chassis packaging has similar mechanical, thermal, and
substrates and boards allow passive resistors and capac- materials considerations found in device and circuit
itors to be buried in the substrate, which frees up ad- board packaging. For APL’s typical spacecraft and for
ditional space on the surface of the substrate. However, most avionics applications, card guides hold the circuit
these built-in components do not have the range of boards by their sides in an aluminum housing, with a
values, tolerances, or performance available from dis- motherboard connecting the different boards (Fig. 9).
crete components. This layout usually reflects the system partitioning to
For high-frequency circuits that are particularly sen- facilitate testing. Card guides ease insertion and remov-
sitive to capacitive coupling, the circuit substrate must al of circuit boards while increasing heat dissipation. To
often be constructed with a special, uniform dielectric facilitate electrical testing, extender cards can be used
material such as Duroid. The Duroid dielectric is a with this layout to probe individual boards while op-
mixture of alumina powder and polytetrafluoroethyl- erating the entire box.
ene that has a controlled, dielectric constant which Traditionally, systems engineering allots each sub-
varies little across the substrate. The copper traces on system or major function its own chassis. Each chassis
these boards are laid out using special rules to optimize would be connected to the system through a power line
circuit performance and minimize reflections. These and data bus and contain its own power supply and data
rules include careful grounding, rounding the corners transfer functions. To conserve space, reduce costs, and
of traces, and choosing trace layouts with matched improve reliability, many newer systems are being pack-
impedance to tune the circuit. aged into a common chassis. These common chassis
Circuit substrate technology has moved from the contain circuit boards for several electronic functions,
traditional flat, rigid boards to flexible substrates and located in one housing, on a common motherboard.
rigid-flex boards, a hybrid of the rigid and flexible tech- By combining many cards and functions into one
nologies. Flexible substrates are made from sheets of housing, redundant power supplies, data transfer
polyimide (e.g., Kapton), laminated with copper foil to circuits, and harnesses are eliminated. This increases
form traces. These may have several layers like rigid packaging density and potentially improves system re-
substrates. Flexible substrates permit rolling and folding liability. Although this packaging concept has advan-
to fit the space available, which has many advantages tages, it complicates testing, heat removal, and system
in the packaging of electronics in constrained areas integration. Because of electromagnetic interference, it

JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 31

M. G. BEVAN AND B. M. ROMENESKO

Figure 8. Four boards and their interconnections are combined into one rigid-flex assembly. The overall assembly size is 13.3 3 8.3 3
6.5 cm.

may not meet the special requirements of radio- Analytical modeling may be performed for each level
frequency and microwave circuits. of packaging to simulate the electrical, mechanical, and
A new development in card cages is the substitution thermal behavior of the system to identify and correct
of graphite-epoxy composite materials for aluminum.18 problems in the design stage. To simplify testing, each
With graphite-epoxy’s high modulus-to-density ratio level of packaging typically isolates a function of the
and high thermal conductivity, this substitution can electronic circuit. Although these levels may not al-
reduce the overall weight of card cages. However, it also ways be distinct, they form the building blocks of the
requires careful layout and analysis to achieve weight total circuit. As circuits become more complex and
savings while meeting thermal dissipation require- miniaturized, electronic packaging needs become more
ments.19 In choosing a composite
card cage, the additional cost of
design, analysis, and fabrication
must be balanced with the poten-
tial weight savings and improve-
ment in thermal performance.

CONCLUSION
Electronic packaging technolo-
gy applies a diverse range of engi-
neering practices to the packaging
of electronic circuits. After the re-
quirements, constraints, and envi-
ronment of the electronic circuit
are considered, the system is parti-
tioned into component, substrate,
and box levels, each one bringing
unique but similar electrical, me- Figure 9. Exploded view of a box and circuit cards used in the Near Earth Asteroid
chanical, and thermal concerns. Rendezvous command/telemetry processor (24.4 3 23.9 3 17.2 cm, 10.9 lb).

32 JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999)

 MODERN ELECTRONIC PACKAGING TECHNOLOGY

5DiStefano, T., and Fjelstad, J., “Chip-Scale Packaging Meets Future Design
challenging, and careful electronic packaging becomes
Needs,” Solid State Technol., pp. 82–90 (Apr 1996).
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Flight Applications,” in Proc. Fifth Int. SAMPE Electronics Conf., pp. 606–614
(18–20 Jun 1991).
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Applied Physics Laboratory Since Its Founding in 1942, Shneidereith and Sons,
Books Baltimore, MD (1983).
Electronic Packaging and Interconnection Handbook, C. A. Harper (ed.), McGraw- 8The Terrier 1B Missile, TG 231-1, JHU/APL, Laurel, MD (Feb 1954).
Hill, New York (1991). 9Clatterbaugh, G. V., and Charles, Jr., H. K., “Thermal and Thermomechnical
Microelectronics Packaging Handbook, 3 vols.: Semiconductor Packaging, Subsystem Analysis and Testing of Electronic Packaging Systems,” Johns Hopkins APL
Packaging, and Technology Drivers, R. R. Tummula, E. J. Rymaszewski, and Tech. Dig. 7(3), 279–283 (Jul–Sep 1986).
A. G. Klopfenstein, (eds.), Chapman and Hall, New York (1997). 10Charles, Jr., H. K., and Petek, J. M., “Known Good Die, Die Replacement
(Rework), and Their Influences on Multichip Module Cost,” in Proc. 48th
Journals IEEE Electronics Components and Technology Conf., Seattle, WA, pp. 909–915
Components, Packaging and Manufacturing Technology, published by IEEE. (May 1998).
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tronics and Packaging Society. APL Tech. Dig. 14(1), 51–67 (1993).
12Charles, Jr., H. K., “Cost Versus Technology Trade-Offs for Multichip
Proceedings
Electronics Components and Technology Conference, sponsored by the CPMT- Modules,” ISHM J. Microelectron. Electron. Packag. 19(3), 295–300 (1996).
13Simmons, R. E., “The Evolution of IBM High Performance Cooling
IEEE, Electronic Industries Association.
International Symposium and Exhibit of Microelectronics, sponsored by The Technology,” IEEE Trans. Compon. Hybrids Manuf. Technol. Part A 18(4),
International Microelectronics and Packaging Society. 805–811 (1995).
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Times, p. 70 (22–29 Dec 1997).
15Solomon, D., Hoffman, P., Brathwaite, G., Robinson, P., and Madelung, T.,
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THE AUTHORS

MATTHEW G. BEVAN holds a B.S. in metallurgy and materials science from

Carnegie-Mellon University and an M.S. and Ph.D. in materials science and
engineering from the University of Maryland, College Park. He joined APL in
1991. Dr. Bevan has worked in the Technical Services Department in both the
Electronics and Mechanical Fabrication Groups, focusing on many areas of
electronic packaging, from semiconductor to subsystem packaging. He has
authored numerous publications in the field of electronic packaging and
reliability. His e-mail address is matthew.bevan@jhuapl.edu.

BRUCE M. ROMENESKO is a Principal Staff physicist in APL’s Materials

Laboratory. He holds a B.S. in mathematics and physics from the University of
Wisconsin and a Ph.D. in experimental solid-state physics from the University
of Maryland. Dr. Romenesko is responsible for the packaging and failure analysis
of high-reliability electronics, including hybrid microcircuits, solder/surface-
mounted devices, and board-level assemblies. He has also been active in
experimentation in microwave hybrid circuit reliability, radiation testing of
electronics used in spacecraft programs, and ball-grid array packaging technolo-
gies. Dr. Romenesko has published over 40 papers in his field. He is currently a
member of the IEEE and IMAPS, and serves as chair of IMAPS’s Interconnec-
tions Subcommittee. His e-mail address is bruce.romenesko@jhuapl.edu.

JOHNS HOPKINS APL TECHNICAL DIGEST, VOLUME 20, NUMBER 1 (1999) 33

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