Bicmos Technology Improvements For Microwave Application
Bicmos Technology Improvements For Microwave Application
Bicmos Technology Improvements For Microwave Application
Abstract—. The third generation of NXP 0.25 µm SiGe and a non-self aligned approach that maintains process
BiCMOS technology (QUBiC4Xi) is presented. The NPN has simplicity; it adds a mask but avoids a lot of critical process
fT /fmax of 216/177 GHz and BVcb0 of 5.2 V. The high-voltage steps (e.g. selective epitaxy or critical CMP steps).
NPN has 12 V BVcb0, and fT /fmax of 80/162 GHz. This is For this generation emphasis was placed on the base link
complemented with an improved MIM capacitor with 1THz region, the emitter-base spacer in particular and the SiGe:C
cutoff frequency and new on-chip isolation structures that
demonstrate a record |S12| of -60 dB at 10 GHz.
layer stack.
The emitter-base region is shown schematically in Figure 1.
Index Terms—HBT, heterojunction bipolar transistor,
substrate isolation, MIM capacitor, BiCMOS, bipolar, Si, The base link is determined by two factors: the emitter-base
SiGe, SiGe:C, TaO5. spacer and a patterned etch-stop layer to facilitate robust
emitter-window patterning.
Emitter
I. INTRODUCTION
SiGe HBT technology and performance has been improved
tremendously in the last decade. This has opened up new Spacer
opportunities for silicon-based technology in the area of Base
microwave and millimeter wave applications. However,
these markets are not mature enough to support high wafer
Collector
volumes and highly integrated solutions that are required
for cost-effective manufacturing. Therefore, NXP has
developed various SiGe process variants that are derived Figure 1 Schematic cross-section of the NPN device with
from the highly successful QUBiC4 0.25µm BiCMOS the base-link area highlighted.
technology family [1, 2]. A high degree of commonality The spacer is most critical because it also determines the
with the parent technology that is running in high volume is scalability of the emitter width. Figure 2 shows two TEM
maintained in all cases. This ensures low cost of wafers and images that compare the new spacer module that was
development, high manufacturability and control, and high introduced to the original spacer.
quality that is proven in high volume.
Here an improved version of QUBiC4X is presented: 150 nm 48 nm
(QUBiC4Xi) [2]. The technology comes with all the
advanced passives of the parent technology and maintains
full compatibility to the 0.25µm CMOS node [1, 3]. Here
we introduce a faster NPN heterojunction bipolar (HBT)
that is discussed in Section II. A modified (single mask
adder) 5fF/µm2 TaO5 MIM capacitor with improved
scalability and reduced top-plate resistance is presented in
Section III. Section IV highlights the outstanding substrate
isolation that can be achieved with the high-resistivity
substrate (200 Ωcm, CZ) and optimized layout techniques.
We will finalize with some conclusions in the last section.
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IEEE BCTM 6.2
The shorter distance under the spacer also leads to 50% SOLT procedure. The measurement was subsequently
reduction in base-link resistance as is shown in Figure 3. deembedded with on-wafer “OPEN” and “SHORT” dummy
The improved scalability facilitates downscaling of the structures.
emitter width from 0.4 µm to beyond 0.25 µm. Figure 4 shows the actual RF characteristics of the devices
99%
listed in Table 1. the highest fT (216 GHz) is obtained with
Cumulative Normal Probablilty [%]
95% the “fast” 4.8 kΩ/sq. stack. Nevertheless, the slower stack
90% has identical fmax and a superior high-voltage device. This
ved
device is fabricated on the same wafer as the 176 GHz fT
Impro
al
70%
in
device. It has a remarkable combination of 12 V breakdown
Orig
50%
(BVcb0) with an fT/fmax of 80/162 GHz.
30%
10%
5%
1%
0 50 100 150 200 250 300
RBlink [Ω µm]
10x0.25x1.0
94
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The RF quality factor (Im(Y12)/Re(Y12) with C between figure). The second structure is similar but has an additional
port 1 and 2) is dominated by the series resistance imposed conductive, grounded guard ring around each pad (b. in the
by limited conductivity of the TiN top plate. This was figure). The third variant is similar to the second, but now
originally compensated with a thick TiN layer and a large the ground domains between the two ports have been
number of vias connecting the top plate to the highly disconnected (c. in the picture).
conductive metal 5. Here we have added a layer of AlCu to
the top plate and reduced the TiN thickness. The overall
stack is: metal 3, TiN, TaO5, TiN, capped by AlCu. The
higher conductivity of AlCu vs. TiN allows for a thinner
overall stack with a 10x reduction in top-plate sheet
resistance.
The RF performance up to 50 GHz of various geometries is
shown in Figure 6.
dG
re
ter
rin
rin
me
ure
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Fig
Gu
Str
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sh
95
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IEEE BCTM 6.2
remarkable. To our knowledge these values exceed have a considerably higher input impedance combined with
anything previously reported [6, 7]. Furthermore, it is high isolation.
surprising, counterintuitive, to see equivalent isolation The pad diameter also plays an important role, the smaller
between P-type and N-type connections above 1 GHz or so. pads (50 µm diameter) have superior isolation that scales
This is clearly the high substrate resistivity at work. roughly with the perimeter at high frequency
(20·log(80/50)~ 4dB).
V. CONCLUSIONS
A highly versatile and low-cost 0.25 µm SiGe:C microwave
technology is presented. It features a scaled NPN with
cutoff frequency of 216 GHz and 177 GHz fmax. A
high-voltage device with 12 V BVcb0, 80 Ghz fT and
162 GHz fmax is also supported. The 5 fF/µm2 MIM
capacitor is very similar to that of the parent technology but
with improved scalability and versatility by introducing
smaller designrules and higher top-plate conductivity. It has
ample RF performance with a cutoff frequency (frequency
Figure 8 Isolation for structures in Table 2 in terms of
where Q reaches 1) of ~ 1 THz and a bandwidth in excess
|S12|, |S21| with 50 Ω system impedance. Left plot: P-
of 10 GHz for a 1 pF capacitor.
type, right plot: N-type.
On-chip isolation of -60dB (S12 magnitude) of a 50µm
The behavior is predominantly capacitive with a slope diameter N-Well or P-Well island is demonstrated, this is
slightly deviating from 20dB/dec, which can be explained among the highest values reported. The highest isolation is
by distributed RC effects. It is somewhat arbitrary to achieved with a combination of deep trench isolation and
present the results in terms of S parameter magnitude. The guardrings with isolated ground domains.
isolation between actual circuit nodes will depend on their
impedance level, which is likely to be different from the ACKNOWLEDGEMENTS
50Ω system impedance. We are very grateful for support by Engineering and Failure
To complement the picture, the input impedance of the analysis groups at NXP Semiconductors East Fishkill. We
isolated pads also needs to be considered. Note that in the also acknowledge support form IMEC P-Line.
particular case of isolation the transfer coefficients are
much smaller than the reflection coefficients thus resulting REFERENCES
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