Singapore p1
Singapore p1
Singapore p1
Programming
2
Schedule
• 9:00-11:00 part I (introduction)
• 11:00-11:15 break
• 11:15-13:00 part II (examples)
• 13:00-14:00 lunch
• 14:00-16:00 part III (advanced topics)
• 16:00-16:15 break
• 16:15-18:00 part IV (lab time)
3
Part I
• Introduction
• Hands-on: getting started with NCSA GPU
cluster
• Anatomy of a GPU application
• Break
4
Introduction
• Why use Graphics Processing Units (GPUs) for
general-purpose computing
• Modern GPU architecture
– NVIDIA
• GPU programming overview
– Libraries
– CUDA C
– OpenCL
– PGI x64+GPU
5
Why GPUs?
1200
Raw Performance Trends
GTX 285
1000
GTX 280
800
GFLOPS
8800 Ultra
600
8800 GTX
NVIDIA GPU
Intel CPU
400
7900 GTX
7800 GTX
200
6800 Ultra Intel Xeon Quad-core 3 GHz
5950 Ultra
5800
0
9/22/02 2/4/04 6/18/05 10/31/06 3/14/08
6
Graph is courtesy of NVIDIA
Why GPUs?
180 Memory Bandwidth Trends
GTX 285
160
GTX 280
140
120
8800 Ultra
GByte/s
100
8800 GTX
80
60
7800 GTX 7900 GTX
40 5950 Ultra
6800 Ultra
20
5800
0
9/22/02 2/4/04 6/18/05 10/31/06 3/14/08
7
Graph is courtesy of NVIDIA
GPU vs. CPU Silicon Use
8
Graph is courtesy of NVIDIA
NVIDIA GPU Architecture
• A scalable array of
multithreaded Streaming
Multiprocessors (SMs),
each SM consists of
– 8 Scalar Processor (SP)
cores
– 2 special function units for
transcendentals
– A multithreaded
instruction unit
– On-chip shared memory
• GDDR3 SDRAM
• PCIe interface
9
Figure is courtesy of NVIDIA
NVIDIA GeForce9400M G GPU
TPC • 16 streaming processors
Geometry controller
SP SP SP SP
SP SP SP SP
SP SP SP SP – 54 GFLOPS in single-
SP SP SP SP
Texture units
Texture L1
chip GDDR3 memory
128-bit interconnect
– 21 GB/s bandwidth
L2 ROP ROP L2
DRAM DRAM
10
NVIDIA Tesla C1060 GPU
TPC 1 TPC 10
• 240 streaming
Geometry controller Geometry controller processors arranged
SM
SMC
SM SM SM
SMC
SM SM
as 30 streaming
I cache
MT issue
C cache
I cache
MT issue
C cache
I cache
MT issue
C cache
I cache
MT issue
C cache
I cache
MT issue
C cache
I cache
MT issue
C cache
multiprocessors
• At 1.3 GHz this
SP SP SP SP SP SP SP SP SP SP SP SP
SP SP SP SP SP SP SP SP SP SP SP SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
provides
SFU SFU
Shared
memory
SFU SFU
Shared
memory
SFU
Shared
memory
SFU SFU
Shared
memory
SFU SFU
Shared
memory
SFU SFU
Shared
memory
SFU
– 1 TFLOPS SP
Texture units Texture units – 86.4 GFLOPS DP
• 512-bit interface to
Texture L1 Texture L1
11
NVIDIA Tesla S1070 Computing Server
supply
Power
Tesla GPU
Tesla GPU
NVIDIA
PCI x16
management
SWITCH
Thermal
PCI x16
NVIDIA
SWITCH
monitoring
System
Tesla GPU
Tesla GPU
4 GB GDDR3
SDRAM 4 GB GDDR3
SDRAM
12
Graph is courtesy of NVIDIA
GPU Use/Programming
• GPU libraries
– NVIDIA’s CUDA BLAS and FFT libraries
– Many 3rd party libraries
• Low abstraction lightweight GPU
programming toolkits
– CUDA C
– OpenCL
• High abstraction compiler-based tools
– PGI x64+GPU
13
CUDA C APIs
• higher-level API called the CUDA • low-level API called the CUDA driver
runtime API API
– myKernel<<<grid size>>>(args); – cuModuleLoad( &module, binfile );
– cuModuleGetFunction( &func,
module, "mykernel" );
– …
– cuParamSetv( func, 0, &args, 48 );
– …
– cuParamSetSize( func, 48 );
– cuFuncSetBlockShape( func, ts[0],
ts[1], 1 );
– cuLaunchGrid( func, gs[0], gs[1] );
14
Getting Started with NCSA GPU Cluster
• Cluster architecture overview
• How to login and check out a node
• How to compile and run an existing
application
15
NCSA AC GPU Cluster
16
GPU Cluster Architecture
• Servers: 32 • Accelerator Units: 32
– CPU cores: 128 – GPUs: 128
ac
(head node)
17
GPU Cluster Node Architecture
IB
• HP xw9400 workstation
QDR IB
– 2216 AMD Opteron 2.4 HP xw9400 workstation
GHz dual socket dual
core
– 8 GB DDR2 PCIe x16 PCIe x16
– InfiniBand QDR
PCIe interface PCIe interface
• S1070 1U GPU
Computing Server T10 T10 T10 T10
Compute node
18
Accessing the GPU Cluster
• Use Secure Shell (SSH) client to access AC
– ssh USER@ac.ncsa.uiuc.edu (User: tra1 – tra54; Password: ???)
[tra1@ac ~]$ _
19
Installing Tutorial Examples
• Run this sequence to retrieve and install
tutorial examples:
cd
cp /tmp/tutorial.tgz .
tar -xvzf tutorial.tgz
cd tutorial
ls
20
Accessing the GPU Cluster
Laptop 1 Laptop 2 Laptop 30
ac
You are here (head node)
21
Requesting a Cluster Node for
Interactive Use
• Run qstat to see what other users do
22
Requesting a Cluster Node
Laptop 1 Laptop 2 Laptop 30
ac
(head node) You are here
7/26/2009 23
Some useful utilities installed on AC
• As part of NVIDIA driver
– nvidia-smi (NVIDIA System Management Interface
program)
• As part of NVIDIA CUDA SDK
– deviceQuery
– bandwidthTest
• As part of CUDA wrapper
– wrapper_query
– showgputime/showallgputime (works from the head
node only)
24
nvidia-smi
Timestamp : Mon May 24 14:39:28 2010
Unit 0: Unit 1:
Product Name : NVIDIA Tesla S1070-400 Turn-key Product Name : NVIDIA Tesla S1070-400 Turn-key
Product ID : 920-20804-0006 Product ID : 920-20804-0006
Serial Number : 0324708000059 Serial Number : 0324708000059
Firmware Ver : 3.6 Firmware Ver : 3.6
Intake Temperature : 22 C Intake Temperature : 22 C
GPU 0: GPU 0:
Product Name : Tesla T10 Processor Product Name : Tesla T10 Processor
Serial : 2624258902399 Serial : 1930554578325
PCI ID : 5e710de PCI ID : 5e710de
Bridge Port : 0 Bridge Port : 0
Temperature : 33 C Temperature : 33 C
GPU 1: GPU 1:
Product Name : Tesla T10 Processor Product Name : Tesla T10 Processor
Serial : 2624258902399 Serial : 1930554578325
PCI ID : 5e710de PCI ID : 5e710de
Bridge Port : 2 Bridge Port : 2
Temperature : 30 C Temperature : 30 C
Fan Tachs: Fan Tachs:
#00: 3566 Status: NORMAL #00: 3584 Status: NORMAL
#01: 3574 Status: NORMAL #01: 3570 Status: NORMAL
… …
#12: 3564 Status: NORMAL #12: 3572 Status: NORMAL
#13: 3408 Status: NORMAL #13: 3412 Status: NORMAL
PSU: PSU:
Voltage : 12.01 V Voltage : 11.99 V
Current : 19.14 A Current : 19.14 A
State : Normal State : Normal
LED: LED:
State : GREEN State : GREEN
25
deviceQuery
CUDA Device Query (Runtime API) version (CUDART static linking)
There is 1 device supporting CUDA
Device 0: "Tesla T10 Processor"
CUDA Driver Version: 3.0
CUDA Runtime Version: 3.0
CUDA Capability Major revision number: 1
CUDA Capability Minor revision number: 3
Total amount of global memory: 4294770688 bytes
Number of multiprocessors: 30
Number of cores: 240
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 16384 bytes
Total number of registers available per block: 16384
Warp size: 32
Maximum number of threads per block: 512
Maximum sizes of each dimension of a block: 512 x 512 x 64
Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
Maximum memory pitch: 2147483647 bytes
Texture alignment: 256 bytes
Clock rate: 1.30 GHz
Concurrent copy and execution: Yes
Run time limit on kernels: No
Integrated: No
Support host page-locked memory mapping: Yes
Compute mode: Exclusive (only one host thread at a time can use this device)
26
wrapper_query
cuda_wrapper info:
version=2
• There are 4 GPUs per
userID=21783 cluster node
pid=-1
nGPU=1 • When requesting a node,
physGPU[0]=2 we can specify how may
key_env_var=
allow_user_passthru=1 GPUs should be allocated
affinity:
GPU=0, CPU=0 2
– e.g., `-l nodes=1:ppn=4`
GPU=1, CPU=0 2 in qsub resources string
GPU=2, CPU=1 3
GPU=3, CPU=1 3 will result in all 4 GPUs
cudaAPI = Unknown allocated
walltime = 10.228021 seconds
gpu_kernel_time = 0.000000 seconds • By default, only one GPU
gpu_usage = 0.00%
per node is allocated
27
Compiling and Running an Existing
Application
• cd tutorial/src1
– vecadd.c - reference C implementation
– vecadd.cu – CUDA implementation
29
Anatomy of a GPU Application
• Host side
• Device side
30
Reference CPU Version
void vecAdd(int N, float* A, float* B, float* C) {
Computational kernel
for (int i = 0; i < N; i++) C[i] = A[i] + B[i];
}
Kernel invocation
vecAdd(N, A, B, C); // call compute kernel
CPU GPU
Host Device
Memory Memory
A gA
B gB
C gC
32
Memory Spaces
• CPU and GPU have separate memory spaces
– Data is moved across PCIe bus
– Use functions to allocate/set/copy memory on GPU
• Host (CPU) manages device (GPU) memory
– cudaMalloc(void** pointer, size_t nbytes)
– cudaFree(void* pointer)
– cudaMemcpy(void* dst, void* src, size_t nbytes, enum
cudaMemcpyKind direction);
• returns after the copy is complete
• blocks CPU thread until all bytes have been copied
• does not start copying until previous CUDA calls complete
– enum cudaMemcpyKind
• cudaMemcpyHostToDevice
• cudaMemcpyDeviceToHost
• cudaMemcpyDeviceToDevice
33
Adding GPU support
int main(int argc, char **argv)
{
int N = 16384; // default vector size
Memory allocation
float *A = (float*)malloc(N * sizeof(float));
on the GPU card
float *B = (float*)malloc(N * sizeof(float));
float *C = (float*)malloc(N * sizeof(float));
34
Adding GPU support
Kernel invocation
vecAdd<<<N/512, 512>>>(devPtrA, devPtrB, devPtrC);
cudaFree(devPtrA);
Copy results from
cudaFree(devPtrB);
device memory to
cudaFree(devPtrC); the host memory
Device memory
free(A);
de-allocation
free(B);
free(C);
}
35
GPU Kernel
• CPU version
void vecAdd(int N, float* A, float* B, float* C)
{
for (int i = 0; i < N; i++)
C[i] = A[i] + B[i];
}
• GPU version
__global__ void vecAdd(float* A, float* B, float* C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
}
36
Introduction to GPU programming
• CUDA programming model
• GPU memory hierarchy
• CUDA C
37
CUDA Programming Model
• A CUDA kernel is executed by threadID
an array of threads
– All threads run the same code (SPMD) …
float x = input[threadID];
float y = func(x);
– Each thread has an ID that it uses output[threadID] = y;
…
to compute memory addresses and
make control decisions
• Threads are arranged as a grid of thread blocks
– Threads within Grid
a block have access Thread Block 0 Thread Block 1 Thread Block N-1
to a segment of …
shared memory Shared memory Shared memory Shared memory
38
Kernel Invocation Syntax
grid & thread block dimensionality
vecAdd<<<32, 512>>>(devPtrA, devPtrB, devPtrC);
Grid
Thread Block 0 Thread Block 1 Thread Block N-1
…
Shared memory Shared memory Shared memory
39
Mapping Threads to the Hardware
• Blocks of threads are transparently • Blocks must be independent
assigned to SMs – Any possible interleaving of blocks
– A block of threads executes on one should be valid
SM & does not migrate – Blocks may coordinate but not
– Several blocks can reside synchronize
concurrently on one SM – Thread blocks can run in any order
Block 2 Block 3
Block 4 Block 5
Each block can execute in any
Block 6 Block 7 order relative to other blocks.
40
Slide is courtesy of NVIDIA
CUDA Programming Model
• A kernel is executed as a Host Device
Grid 1
grid of thread blocks
– Grid of blocks can be 1 or 2- Kernel Block
(0, 0)
Block
(1, 0)
Block
(2, 0)
1
dimentional
– Thread blocks can be 1, 2, or Block
(0, 1)
Block
(1, 1)
Block
(2, 1)
3-dimensional
• Different kernels can have
Grid 2
different grid/block
Kernel
configuration 2
41
Slide is courtesy of NVIDIA
GPU Memory Hierarchy
• Global (device) memory
– Accessible by all threads as well as host (CPU)
– Data lifetime is from allocation to deallocation
Device 0
memory
Device 1
memory
42
GPU Memory Hierarchy
• Global (device) memory
Kernel 0
Thread Block 0 Thread Block 1 Thread Block N-1
…
Per-device
Global
Kernel 1 Memory
Thread Block 0 Thread Block 1 Thread Block N-1
43
GPU Memory Hierarchy
• Local storage • Shared memory
– Each thread has own local – Each thread block has own
storage shared memory
– Mostly registers (managed by • Accessible only by threads
the compiler) within that block
– Data lifetime = thread lifetime – Data lifetime = block lifetime
Thread Block
Per-block
Per-thread
shared
local memory
memory
44
GPU Memory Hierarchy
• 1D grid Grid of 2 thread blocks
block 0 block 1
– 2 thread blocks
Shared memory Shared memory
• 1D block
registers registers registers registers
– 2 threads
thread 0 thread 1 thread 0 thread 1
Global memory
Host memory
Constant memory
45
GPU Memory Hierarchy
Host Device
CPU DRAM GPU
Multiprocessor
Multiprocessor
local Multiprocessor
chipset
global registers shared
memory
constant
DRAM texture constant and texture caches