Journal of ELECTRICAL ENGINEERING, VOL. 57, NO.

5, 2006, 285290

A NEW MODELLING AND CONTROL ANALYSIS OF

AN ADVANCED STATIC VAR COMPENSATOR USING
A THREELEVEL (NPC) INVERTER TOPOLOGY

Mustapha Benghanem Azeddine Draou

This paper presents a study of the dynamic performance analysis of an Advanced Static Var Compensator (ASVC) using
a three-level voltage source inverter. The analysis is based on the modelling of the system in the d - q axis. The dynamic
behaviour of the system is analysed using P-spice (Simulation Program with Integrated Circuit Emphasis) as a simulation
program. Various transient simulation results are reported and discussed.
K e y w o r d s: P-spice, advanced static var compensator

1 INTRODUCTION parallel to the segment series capacitor. Although the

TCSC is primarily used for regulating the power flow
Real and reactive powers on a transmission line in an
integrated network are governed by the line impedance, through varying its effective reactance inserted in series
voltage magnitudes, the angle difference at the line ends, with the transmission line, it may also be used for volt-
and the role the line is playing in maintaining network age stabilization. In this case, the output reads the termi-
stability under dynamic contingencies. Power transfer in nal voltage within a tight band. Recently, voltage source
most integrated transmission systems is constrained by converters using GTO thyristor have been developed to
transient stability, voltage stability, and/or power stabil- operate as static VAR compensators [57]. These convert-
ity. Reactive power (VAR) compensation or control is an ers are known as ASVC. Such converters may resemble
essential part in a power system to minimize power trans- the operation of synchronous condensers but in a static
mission losses, to maximize power transmission capabil- manner. For these devices, a converter transformer is al-
ity, and to maintain the supply voltage. It is increasingly ways needed to complement the function of the power
becoming one of the most economic and effective solutions electronic switches to perform system VAR compensa-
to both traditional and new problems in power transmis- tion and may also be used to connect the device to the
sions systems. It is a well-established practice to use reac- high voltage bus. The converter supplies reactive power to
tive power compensation to control the magnitude of the the network by increasing the synthesized inverter output
voltage at a particular bus bar in any electric power sys- voltage. Similarly, the ASVC absorbs VARs from the net-
tem. In the past, synchronous condensers, mechanically work by reducing the output voltage below the network
switched capacitors and inductors, and saturated reactors voltage, ie, no large power components such as capacitor
have been applied to control the system voltage in this banks or reactors are used. Only a small capacitor is em-
manner [1, 2]. ployed to provide the required reference voltage level to
Since the late 1960s, thyristor controlled reactor (TCR) the inverter. In contrast to the TCR/FC or TCR/TSC
devices together with fixed capacitor FC or thyristor schemes bulky and expensive passive elements are not re-
switched capacitor (TSC) have been used to inject or ab- quired. The possibility of PWM voltage source convert-
sorb reactive power [3, 4]. ers with a high switching frequency for reactive power
Series compensation is the control of the equivalent compensation has also been reported [8, 9]. However, the
line impedance of a transmission line. The introduction high switching frequency operation of GTO is not avail-
of external components (either capacitive or inductive) able. Recently, in order to apply large-scale reactive power
is used to change the apparent reactance of the line.
compensation, new SVC systems with a low switching fre-
The controllable series compensator such as the thyris- quency PWM operation have been reported [1012]. The
tor controlled series compensation (TCSC) has been de- conventional GTO inverters have a limitation of their dc
veloped to change the apparent impedance of a line by
link voltage about 2 kV. Hence, the series connections of
either inductive or capacitive compensation, facilitating
the existing GTO thyristors have been essential in real-
active power transfer control. The thyristors control the
conduction period of the reactor to vary the overall ef- izing high voltage about 4 kV. So there have been great
fective impedance of the circuit. The TCSC suffers from interests in the multilevel level inverter topology, which
the disadvantages that it generates low order harmonic can overcome the series connection problems.
components into the power system. TCSCs are usually Recently, the multilevel pulse width modulation con-
connected in series to conventional line series capacitors. verter topology has drawn tremendous interest in the
They may consist of one or several identical modules. power industry since it can easily provide the high power
Each module has a small thyristor controlled reactor in required for high power applications for such uses as static

Applied Power Electronics Laboratory, Faculty of Electrical Engineering, Dept. of Electrotechnics, University of Sciences and Tech-
nology of Oran, BP 1505 El Mnaouar (31000 Oran), Algeria, E-mail: a draou@yahoo.co.uk, mbenghanem69@yahoo.fr

c 2006 FEI STU

ISSN 1335-3632
286 M. Benghanem A. Draou: A NEW MODELING AND CONTROL ANALYSIS OF AN ADVANCED STATIC VAR . . .

made up of twelve power GTOs with antiparallel diodes,

which is connected to the three-phase supply through a
reactor X of small value. Two capacitors are connected
to the dc side of the converter. The structure of one leg of
the inverter itself is made up of four pairs of diode-GTO
forming a switch and two diodes allowing to have the zero
level point of the inverter output voltage.
The operation principles of the system can be ex-
plained by considering the per-phase fundamental equiv-
alent circuit of the ASVC system as shown in Fig. 2. In
this figure, Ea1 is the ac mains voltage source. Ia1 and
Va are the fundamentals components of current and out-
put voltage of the inverter supply respectively. The ASVC
is connected to the AC mains through a reactor L and
a resistor R representing the total loss in the inverter.
As shown in Fig. 3, by controlling the phase angle of
Fig. 1. Power circuit of the ASVC. the inverter output voltage, the dc capacitor voltage Uc
can be changed. Thus, the amplitude of the fundamental
component Ea1 can be controlled.

3 MATHEMATICAL MODEL
OF THE ASVC [14]

Figure 4 shows a simplified equivalent circuit of the

Fig. 2. Per-phase fundamental equivalent circuit. ASVC. Using matrix form, the mathematical model is
given by:
R
L 0 0

ia ia va ea
d 1
ib = 0 R 0 ib + vb eb (1)

dt L L
ic 0 0 R ic vc ec
L

Fig. 3. Phasor diagram for leading and lagging mode.

The model of the inverter output voltage is given by

ea 2 1 1 S1A S2A
1
eb = 1 2 1 S1B S2B Uc1
VAR compensation, active power filters, and the control
3
of large motors by high power adjustable frequency drives. ec 1 1 2 S1C S2C

The most popular structure proposed as a transformer-
S3A S4A

less voltage source inverter is the diode clamped converter

S3B S4B Uc2 . (2)
based on the neutral point clamped (NPC) converter pro-
S3C S4C

posed by Nabae [13]. It has the advantages that the block-
ing voltage of each switching device is one half of dc link
voltage and the harmonics contents output voltages are
far less than those of a two-level inverter at the same
switching frequency. Each alternative has its technical
and economical advantages, limitations, and drawbacks,
and it is the scope of this paper to present the modelling
and analysis of this new type of inverter used for static
VAR compensation.
The main purposes of the paper are not only to illus-
trate the model of the ASVC using N.P.C inverter, but
also to describe the closed loop reactive power controller
design. Finally, the P-spice implementation of ASVC Fig. 4. Equivalent circuit of the ASVC
model is included as well as some simulation results un-
der various transient conditions of the proposed ASVC
model and its control. With:
Ski : The switching function, is either 1 or 0 correspond-
2 OPERATING PRINCIPLE ing to on and off states of the switch Qki respec-
tively.
The static VAR compensator (ASVC) which uses a
three-level converter of the voltage source type is shown K : Names of arms (A, B ,C).
in Fig. 1. The main circuit consists of a bridge inverter i : number of switches of one arm (i = 1, 2, 3, 4)
 Journal of ELECTRICAL ENGINEERING 57, NO. 5, 2006 287

Equation (9) gives the inverter voltage.

eA
EABC = eB = F Uc (9)
ec
F is the commutation function defined by equation (10)

r sin(t + )
2
F = D sin(t 2/3 + ) (10)
3
sin(t + 2/3 + )
p
IM = 2/3D (11)
D is the modulation index in the Park axis. The voltage
supply equation in the dq frame is given by (12)

Fig. 5. Three-level PWM sin
Vqd0 = P VABC = VL cos (12)
0
The DC side currents are given by
and for the inverter voltage we obtain
IC1 = S1A S2A iA + S1B S2B iB + S1C S2C iC
0
(3)
IC2 = S3A S4A iA + S3B S4B iB + S3C S4C iC Eqd0 = P EABC = D UC (13)
0
IC0 = IC1 + IC2 (4)
Equation (1) transformed in dq frame gives equation (15)
and the DC side capacitor voltages are given by   
d iq R/L
 
iq

1 vq eq

= + . (14)

d UC1
 
1 IC1
 dt id R/L id L vd ed
= . (5)
dt UC2 C IC2 Substituting equations (12) and (13) in (14) we get
      
d iq R/L iq 1 VL sin
The dynamic model of the power circuit of an ASVC in = + .
the abc reference frame is given by equations (1) to (5). dt id R/L id L VL cos DUC
(15)
3.1 DQ Frame For the DC side of the inverter we may get the following
Parks transformation matrix (6) is used to develop equations. The DC current is given by
the time-invariant form in a two-axis (d - q - o ) rotating Ic1 + Ic2 = 2Ic = F iabc (16)
reference frame under the following assumptions:
all switches are ideal, and
the source voltages are balanced, iabc = P 1 iqdo = P iqdo (17)
the total losses in the inverter are represented by
lumped resistor R , iq
the total harmonic contents caused by switching action 2Ic = F P iqdo = [ 0 D 0 ] id = Did . (18)
are negligible. io
The capacitors voltages are given by:
cos(t + ) cos t 2 dUC iC


3 +
= (19)
r
2 2 dt C
P = sin(t + ) sin t 3 +
3 1 1 combining equations (19) and (20) we get (21)
2 2
dUC Did
cos(t + 2

3 + )
= (20)
dt 2C
sin(t + 2
3 + ) . (6)

and the reactive power delivered by ASVC is given by the
1 relation (21) in the DQ Frame:
2
Qc = Vq id Vd iq . (21)
Thus we write equation (7)
Combining all equations we obtain
Uc1 = Uc2 = Uc

iq R/L 0 iq
(7) d
Ic1 = Ic2 = Ic id = R/L D/L id +
dt
Uc 0 D/2C 0 Uc
The AC mains voltage is defined by (8)
VL sin

1
r VL cos . (22)
vA sin(t) L
2 0
VABC = vB = VL sin(t 2/3) (8)
3 In equation (22) the control parameter is defined in the
vC sin(t + 2/3)
form of sin and cos . Thus the system is nonlinear. In
where VL is the rms line voltage. the next section we establish a linear model.
288 M. Benghanem A. Draou: A NEW MODELING AND CONTROL ANALYSIS OF AN ADVANCED STATIC VAR . . .

Fig. 6. Main circuit and control block diagram.

3.2 Linear model 3.3 Regulator synthesis

From equation (28) we calculate the transfer function
of the system equation (29).

QC (s) A(s)
G(s) = = ,
(s) B(s)
V 2h R D2 i
A(s) = L s2 + s + , (29)
L L 2LC
Fig. 7. Simplified Pspice model of a switch and its antiparallel 2R 2 nh R i2 D2 o D2 R
B(s)=s3 + s + + + 2 s + .
diodes. L L 2LC 2L2 C
To achieve an easier design of the control, equations The ASVC control scheme is illustrated in the block dia-
(22) must be linearized under the following assumptions. gram of Fig. 5. First, a conventional PI controller is used
Disturbance is small. to study the dynamic behaviour of the system [15].
The second-order terms are dropped.
The quiescent operating o is near zero. 3.4 PWM three-level control strategy
The annotation is introduced to indicate disturbed Figure 6 shows the triangular-sinusoidal control used
values. in this work [16]. We used the following signals.
Equations (23) to (27) are substituted in equation (22) The reference signals Vref ,
The Triangular carrier VA ,
iq = iqo + iq (23) and the gates signals, VAM phase A voltage to middle
point of capacitors. The switching signals patterns are
id = ido + id (24) generated in this manner:
UC = UCO + UC (25) FOR k = A, B ,C DO
= O + (26) If (vref (k)> 0) and (vref (k) Vc)
Then Sk1 = 1, Sk2 = 1, Sk3 = 0, Sk4 = 0.
Qc = Qco + Qc (27) Elseif (vref (k)?0) and (vref (k)? VA)
Then Sk1 = 0, Sk2 = 0, Sk3 = 1, Sk4 = 1.
we obtain equation (28) in the state space. Else Sk1 = 0, Sk2 = 1, Sk3 = 1, Sk4 = 0
End DO

i R/L 0 iqo
d qo
ido = R/L D/L ido + 4 PSPICE MODELLING
dt
Uco 0 D/2C 0 Uco We have chosen to model the GTO in a simplified form,

V resistor with a big value if the GTO is OFF and a small
1 L
0 (28) value if GTO is ON. This pinciple is illustrated in Fig. 7
L [17]. Figure 8 shows the PWM generating method of gate
0
signals, and Fig. 9 shows this circuit transformed under
iqo P-spice.
Qc = [ VL 0 0 ] ido The schemes of Figs 1 and 9 are used to establish a
Uco P-spice program (using Microsim Evaluation Version 6.0)
of the power circuit and control circuit, respectively.
 Journal of ELECTRICAL ENGINEERING 57, NO. 5, 2006 289

Fig. 8. PWM generator circuit. Fig. 9. Scheme circuit of PWM generator under Pspice.

Fig. 10. Simulated reactive power response.

Fig. 11. Simulated current and voltage waveforms.

Fig. 12. Simulated inverter DC Bus voltage. Fig. 13. Simulated inverter current in dq frame.

P-spice. Computer simulation is carried out using the

system parameters given by [17]: f = 60 Hz, W = 2f ,
VL = 550 V, R = 0.4 , L = 10 mH, C = 1000 F ,
MI (Modulation Index)=1.2.
Based on the linear model described above and using
root locus technique the parameters of the controller are
found to be [15]. Kp = 105 , Ki = 1.7 104 . The am-
plitude of the reference was adjusted to cause the system
to swing from lagging mode to leading mode.
Figure 10 shows the simulated reactive power delivered
by ASVC due to a reference change from 20 kVAR lag-

ging to 20 kVAR leading. Figure 11 shows the simulated
Fig. 14. Variation of the control angle . current and voltage waveforms to step reference of reac-
tive power. The DC side response to the same change is
depicted on Fig. 12 we notice a fluctuation of voltages Uc1
5 SIMULATION RESULTS and Uc2 around an average value. The ASVC currents in
To check the validity of the model described above a the dq frame are represented in Fig. 13. Figure 14 shows
set of simulation tests have been carried out to analyse the the waveform of the control parameter delivered by the
system under steady state and transient conditions using regulator PI.
 290 M. Benghanem A. Draou: A NEW MODELING AND CONTROL ANALYSIS OF AN ADVANCED STATIC VAR . . .

6 CONCLUSION [13] NABAE, A.TAKAHASHI, I.AKAGI, H. : A New Neutral

Point Clamped PWM Inverter, IEEE Trans. on IA. IA-17 No.
A study and mathematical modelling of the dynamic 5 (Sep/Oct 1981), 509517.
performance analysis of an Advanced Static Var Compen- [14] CHO, G. C.CHOI, N. S.RIM, C. T.CHO, G. H. : Mod-
sator (ASVC) using three-level voltage source inverter has eling, Analysing and Control of Static Var Compensator Us-
been presented in this paper. The dynamic behaviour of ing Three-Level Inverter, IEEE Ind. Soc. Annu. Meet. 1992,
the system was analysed using P-spice through a set of pp. 837843.
simulation tests which have lead to the design of an inex- [15] TAHRI, A.DRAOU, A.BENGHANEM, M. : A Fast Cur-
pensive controller for reactive power applications. From rent Strategy of a PWM Inverter Used for Var Compensation,
Proceeding vol. 1 IECON98.
the results of the simulations and the mathematical mod-
[16] DRAOU, A.BENGHANEM, M.TAHRI, A.KOTNI, L. :
elling developed in this paper, we have directed our future A New Approach to Modelling Advanced Static Var Compen-
research work to add time domain voltage source model sator, Conf. Rec IEEE/CESA Vol. 3, No. 7, 578, Hammamet,
of arc furnace. This may lead to design a faster and ro- Tunisia, April 1998.
bust control to reduce VAR caused by the rapid variation [17] BERKOUK, E. M.ROMDHANE, Y. B.MANESSE, G. :
in the arc furnace current. Knowledge and Control Models for Three-Level Voltage Invert-
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[18] RAMSHAW, R.SCHUURMAN, D. : Pspice Simulation of
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[4] AKAGI, H.KANAZAWA, Y.NABAE, A. : Instantaneous degrees from the University of Sciences and Technology of
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active member of the Applied Power Electronics Laboratory.
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of Harmonic Elimination PWM in Power Control, IEEE Trans. Azeddine Draou was born in Maghnia, Algeria in 1955.
Ind. Appl. Electronics Letters 32 No. No 12 ( 4th June 1987). He received the BEng degree from Sheffield University, UK
[7] MORAN, L.ZIOGAS, P. D.JOOS, G. : Analysis and Design in 1980, the MSc degree from Aston University in Birming-
of a Synchronous Solid-State Var Compensator, IEEE Trans. on ham, UK in 1981, and the PhD degree from Tokyo Institute
Ind. Appl. IA-25 No. 4 (July/Aug 1989), 598608. of Technology, Japan in 1994 all in Electrical Engineering.
[8] ENJETI, P. N.ZIOGAS, P. D.LINDSAY, J. F. : Pro- From 1982 to 1986 he was a senior Engineer for Sonatrach
grammed PWM Techniques to Eliminate Harmonics: A Criti- Ammonia plant, Arzew, Algeria. In 1986, he joined the de-
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[9] JOOS, G.MORAN, L.ZIOGAS, P. D. : Performance Anal- to assistant professor in 1989, Associate professor in 1996. He
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papers in technical journals and conference proceedings. He
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has also co-authored in the Power Electronics Handbook
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Tran. Industry Application 28 No. 3 (May/June 1992), 558566. edited by Dr M. H. Rashid, with Academic Press in 2001. He
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AC Transmission Systems, IEE. Proceed. C 139 No. 4 (July His main area of research includes power electronics, static
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[12] HOLTZ, J. : Pulse Width Modulation A Survey, IEEE Trans. AC drives, UPFC and FACTS devices. Dr Draou is a Senior
on IE. 39 No. 5 (Dec 1992), 410420. member of the IEEE/PES, IES, IAS societies.