Microgrid Power Quality Enhancement Using A Three-Phase Four-Wire Grid-Interfacing Compensator PDF
Microgrid Power Quality Enhancement Using A Three-Phase Four-Wire Grid-Interfacing Compensator PDF
Microgrid Power Quality Enhancement Using A Three-Phase Four-Wire Grid-Interfacing Compensator PDF
AbstractThis paper presents a three-phase four-wire grid-in- will open and isolate the microgrid. However, when the utility
terfacing power quality compensator for microgrid applications. voltages are not so seriously unbalanced, the separation device
The compensator is proposed for use with each individual dis- will remain closed, subjecting the microgrid to sustained un-
tributed generation (DG) system in the microgrid and consists
of two four-phase-leg inverters (a shunt and a series), optimally balanced voltages at the point of common coupling (PCC), if
controlled to achieve an enhancement of both the quality of no compensating action is taken. Such an unbalance in voltages
power within the microgrid and the quality of currents flowing can cause increased losses in motor loads and abnormal opera-
between the microgrid and the utility system. During utility grid tion of sensitive equipment.
voltage unbalance, the four-phase-leg compensator can compen- An obvious solution is to balance the voltages within the
sate for all the unwanted positive-, negative-, and zero-sequence
voltagecurrent components found within the unbalanced utility. microgrid using some voltage regulation techniques. However,
Specifically, the shunt four-leg inverter is controlled to ensure large unbalanced currents can flow between the unbalanced
balanced voltages within the microgrid and to regulate power utility grid and microgrid due to the very low line impedance in-
sharing among the parallel-connected DG systems. The series terfacing both grids, if only the microgrid voltages are regulated
inverter is controlled complementarily to inject negative- and [1]. This flow of large currents can overstress semiconductor
zero-sequence voltages in series to balance the line currents, while
generating zero real and reactive power. During utility voltage devices within the interfacing inverters and the distribution
sags, the series inverter can also be controlled using a newly lines, and is expected to worsen during utility voltage sags when
proposed fluxcharge current-limiting algorithm to limit the flow the voltage differences between the utility grid and the micro-
of large fault currents between the micro- and utility grids. The grid increase. For low voltage distribution, where microgrids
performance of the proposed compensator has been verified in are usually constructed with a four-wire configuration to supply
simulations and experimentally using a laboratory prototype.
both single-phase and three-phase loads, the problem is further
Index TermsFault current limitation, four-phase-leg in- complicated by the flow of zero-sequence currents through the
verter, microgrid, power quality compensator, sequence volt-
ages/currents. line and neutral conductors.
To mitigate the above-mentioned complications, this paper
proposes a grid-interfacing power quality compensator for
I. I NTRODUCTION three-phase four-wire microgrid applications. The proposed
compensator is to be used with each individual distributed
M ICROGRIDS can generally be viewed as a cluster of
microgenerators connected to the mains utility grid,
usually through some voltage-source-inverter (VSI)-based in-
generator (DG), and it consists of two optimally controlled
four-phase-leg inverters (a shunt and a series as in Fig. 1).
terfaces. Concerning the interfacing of a microgrid to the utility Operating together, the two four-leg inverters can compensate
system, an important area of study is to investigate the impact for all the unwanted positive-, negative-, and zero-sequence
of unbalanced utility grid voltages and utility voltage sags, voltages/currents within the system, enhancing both the quality
which are two most common utility voltage quality problems, of power within the microgrid and the quality of current flowing
on the overall system performance. As a common practice, if between the microgrid and the utility. During utility voltage
the utility grid voltages are seriously unbalanced, a separation sags, the compensator can also be controlled to limit the flow of
device, connected between the microgrid and the mains grid to large fault currents using a newly proposed fluxcharge current-
provide isolation in the event of mains faults as in Fig. 1(a), limiting algorithm. The proposed system has been tested in
simulations and experimentally using a laboratory hardware
prototype. Lastly, to assist readers in identifying objectives of
Paper IPCSD-05-064, presented at the 2004 Industry Applications Society the paper, Table I, summarizing the compensator functionalities
Annual Meeting, Seattle, WA, October 37, and approved for publication in the and control features, is included.
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power
Converter Committee of the IEEE Industry Applications Society. Manuscript
submitted for review October 15, 2004 and released for publication August 26, II. T HREE -P HASE F OUR -W IRE G RID -I NTERFACING
2005.
The authors are with the Center for Advanced Power Electronics, School P OWER Q UALITY C OMPENSATOR
of Electrical and Electronic Engineering, Nanyang Technological University,
Singapore 639798 (e-mail: emahinda@ntu.edu.sg). Fig. 1 shows the general layout of the proposed grid-inter-
Digital Object Identifier 10.1109/TIA.2005.858262 facing power quality compensator. The compensator consists
Fig. 1. Proposed microgrid compensator. (a) Overall system structure. (b) Inverter topology.
TABLE I
POWER COMPENSATOR FEATURES AND CONTROL STRUCTURES
of two four-phase-leg inverters, namely inverter A (shunt) and task would require inverter B to carry relatively large current
inverter B (series). The main functions of inverter A are to with a high compensating voltage appearing across it, implying
maintain a set of balanced sensitive load voltages within the that inverter B must have high power rating, too.
microgrid even under unbalanced load and grid voltage con- It is commented that the operational principles of the
ditions, generate and dispatch power, share the power demand compensator presented here are different from those of a
optimally with the other parallel-connected DG systems when unified power quality conditioner (UPQC), which is usually
the microgrid islands, and synchronize the microgrid with the constructed using a shunt and a series three-phase-leg inverter.
utility system at the instant of connection. In addition, being For a UPQC, the series three-leg inverter injects voltages to
connected directly to the microsource, inverter A must have maintain a set of balanced distortion-free voltages at the load
sufficiently high power capacity with rated voltage and head- terminals, while the shunt three-leg inverter injects harmonic
room for current higher than the rated value (in fault conditions) compensating currents into the alternating current (ac) system
in order to continuously condition the routine energy supplied to shape the supply currents drawn by the UPQC-conditioned
by the microsource (similar to most shunt inverter applications loads as balanced sinusoids. In addition, the UPQC is usually
on power systems). On the contrary, the main functions of designed to function with zero real power flow through it during
inverter B are to maintain a set of balanced line currents by in- steady state to minimize the size of the direct current (dc)
troducing negative- and zero-sequence voltages to compensate link energy storage capacitor [2]. These control objectives of a
for the grid voltage unbalance, and to limit the flow of large UPQC are obviously different from those of the proposed four-
fault currents during utility voltage sags. This second control phase-leg compensator, where inverter A is used for voltage
LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1709
+
Note that the first two rows of T0 , Tdq0 , and Tdq0
resemble the commonly used three-phase abc to
to dq transformation. Equations (1)(8) can therefore be
viewed simply as an extension from the three-phase abc
to to dq transformation with only an independent
zero-sequence row added. It would therefore be convenient to
control the dq voltages independently from the zero-sequence
voltages, as indicated in Fig. 2(b) with the zero-sequence con-
trol path drawn external to the dotted box enclosing the dq
control paths.
To achieve zero steady-state errors when controlling the
positive- and negative-sequence dq voltages, two PI con-
trollers are used along the positive- and negative-sequence dq
control paths. Practically, the implementation of these dq con-
trollers can be computationally inefficient due to the numerous
coordinate frame transformations needed [6]. A more efficient
form of the voltage controllers can be derived by transforming
both the positive- and negative-sequence PI controllers to the
stationary frame using either the state-space or frequency-
domain technique [5], [6]. Performing this inverse transforma-
tion with kp+ = kp = kp and ki+ = ki = ki , the frame
voltage controllers can be expressed as
2kp + s22k+
is
2 0
. (9)
0 2kp + s22k+
is
2
TABLE II
SYSTEM PARAMETERS
cycle filtering would be the overall poorer controller transient To confirm the robustness of the inverter B control scheme, a
response. Also shown in Fig. 5(b) are measures taken to de- typical distribution system where the line reactance is either
couple the d- and q-control paths (indicated by dotted lines the same or smaller than the line resistance [7] is consid-
in the figure) to arrive at three decoupled d-, q-, and 0-axis ered. With the series transformer leakage impedance lumped
control paths, which can be tuned independently. The outputs together with the line impedance for simplicity, and even with
of this outer reference voltage generator, consisting only of an onerous condition of XLine = (2f )LLine = 2RLine for
negative- and zero-sequence components, are then transformed this distribution system, the stability condition (13) becomes
back to the 0 frame and fed into the inner voltage Lf (2ki RLine / 2 f 2 ) > 0, which can easily be met. Con-
control loop. sequently, (14) can also be met since the term in (14) is
The block representation of the inner voltage loop is shown now minimized by having a relatively larger denominator than
in Fig. 5(c), where P + resonant controllers are used along the numerator (the numerator is usually small due to the presence
0 control paths. The use of P + resonant controllers in of a microfarad capacitive term Cf ).
the inner control loop will force the filtered capacitor voltages Once the design of the inner voltage loop is completed, the
VC of the series inverter to track the demanded negative- next step is to design the outer reference voltage generator
and zero-sequence reference voltages VC with zero steady- in the negative synchronous reference frame. In the negative
state errors and eliminate any positive-sequence component synchronous dq frame, positive-sequence currents, which
since its reference value is kept at zero for the series inverter. appear as ac signals at twice the fundamental frequency, should
The series inverter therefore injects only negative- and zero- be removed using half fundamental cycle filtering [8] to
sequence voltages into the system to maintain a set of balanced enhance the robustness of the control loop. Another consider-
line currents with no real and reactive power generation (or ation is to identify an alternative nonideal resonant controller
absorption) in the steady state. [see Fig. 5(b)] for use along the zero-sequence control path,
Note that an inner filter inductor current loop can be added whose transfer function is expressed as [6]
to the voltage control loop to give a better dynamic response.
However, due to the slow response of the outer reference volt-
age generation loop, a single inner voltage loop is considered 2ki0 cut s
kp0 + (15)
sufficient, and this loop can reasonably be represented by a s2 + 2cut s + 2
unity gain when designing the control scheme.
where cut represents the low-frequency cutoff. An example
B. Closed-Loop Transfer Functions bode plot of (15) is given in Fig. 3(b), which obviously shows
As a common practice, the design of the proposed control a wider resonant peak with a large finite gain, as compared to
algorithm for the series inverter begins with the inner voltage that of (9) given in Fig. 3(a). Equation (15) is therefore less
loop in the 0 frame. Analyzing Fig. 5(c) with Kinv = sensitive to frequency fluctuation, and the steady-state error
2/Vdc , the closed-loop transfer function of the inner voltage would be still kept relatively small. This nonideal controller
loop can be derived as in (12), shown at the bottom of the should generally be used in cases with resonant frequency
page, where RLine and LLine , which normally represent line variations, and it is particularly applicable to the experimental
resistance and inductance, are here lumped together with the series inverter implemented in Section VIII. In that prototype,
series transformer winding parameters for convenience. When the inverter neutral phase-leg is asynchronously switched by
performing zero-sequence analysis, neutral line parameters are an external analog comparator and triangular signal genera-
also lumped into RLine and LLine . tor due to the shortage of synchronized PWM channels on
To maintain stability, the Rouths stability criteria of (13) and the dSPACE DS1103 controller card. This causes slight fre-
(14) must be met for the inner voltage loop quency variation in the neutral line current waveform, whose
effect is nullified by the 0 transformation matrix in
2ki L2Line (4) along the outer negative-sequence PI control path. How-
Lf > 0 (13) ever, along the 0-axis control path, its effect is not nullified,
RLine
2kp RLine + 2ki LLine + RLine + Lf Cf RLine 2 and, therefore, the nonideal P + resonant compensator with a
wider resonant bandwidth is needed for reducing the system
2 sensitivity level.
2ki Lf Cf RLine + L2f Cf RLine 2
2k L2Line
> 0. (14) Incorporating these fine-tuning schemes, the final closed-
Lf Ri Line loop transfer functions of the proposed control algorithm can
GVcl = kp LLine s3 + (2kp RLine + 2ki LLine )s2 + (2kp 2 LLine + 2ki RLine )s + 2kp 2 RLine
Lf Cf LLine s5 + Lf Cf RLine s4 + (Lf + LLine + 2kp LLine + Lf Cf LLine 2 )s3 + (2kp RLine + 2ki LLine
+ RLine + Lf Cf RLine 2 )s2 + (2kp + 1) 2 LLine + 2 Lf + 2ki RLine s + (2kp + 1) 2 RLine (12)
LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1713
kp0 s2 + 2cut kp0 + ki0 s + 2 kp0
GIcl = (17)
LLine s3 + 2cut LLine + RLine + kp0 s2 + 2 LLine + 2cut RLine + 2cut kp0 + 2cut ki0 )s + 2 (RLine + kp0
1714 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005
Fig. 11. Simulated filtered voltages generated by series inverter B. (a) abc
Fig. 9. Simulated waveforms of (a) mains grid voltages, (b) abc frame frame. (b) 0 frame (zoomed-in view in the steady state).
sensitive load voltages in the microgrid, and (c) 0 frame sensitive load
voltages in the microgrid.
Fig. 12. Simulated line currents with series inverter B. (a) abc frame.
(b) Negative dq0 frame.
Fig. 10. Simulated line currents without series inverter B. (a) abc frame.
(b) Negative dq0 frame.
Fig. 14. Simulated waveforms of (a) mains grid voltages and (b) abc
frame sensitive load voltages in the microgrid.
Fig. 16. Simulated waveforms of (a) real power supplied by shunt inverter A,
(b) reactive power supplied by shunt inverter A, (c) real power supplied by
series inverter B, and (d) reactive power supplied by series inverter B.
Fig. 19. Experimental line currents with series inverter B. (a) abc frame.
Fig. 17. Experimental waveforms of (a) mains grid voltages, (b) abc (b) Negative dq0 frame.
frame sensitive load voltages in the microgrid, and (c) 0 frame sensitive
load voltages in the microgrid.
Fig. 21. Experimental waveforms of (a) mains grid voltages and (b) abc
frame sensitive load voltages in the microgrid.
Fig. 23. Experimental waveforms of (a) real power supplied by shunt inverter
A, (b) reactive power supplied by shunt inverter A, (c) real power supplied by
series inverter B, and (d) reactive power supplied by series inverter B.
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LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1719
Yunwei Li (S04) received the B.Eng. degree in elec- Poh Chiang Loh (S01M03) received the B.Eng.
trical engineering from Tianjin University, Tianjin, (Hons.) and M.Eng. degrees from the National Uni-
China, in 2002. He is currently working toward the versity of Singapore, Singapore, in 1998 and 2000,
Ph.D. degree in the School of Electrical and Elec- respectively, and the Ph.D. degree from Monash Uni-
tronic Engineering, Nanyang Technological Univer- versity, Monash, Australia, in 2002, all in electrical
sity, Singapore. engineering.
From February to July 2005, he was with the During the summer of 2001, he was a Visiting
Institute of Energy Technology, Aalborg University, Scholar at the Wisconsin Electric Machine and Pow-
Aalborg, Denmark, as a Visiting Scholar. er Electronics Consortium, University of Wisconsin,
Mr. Li is a member of the IEEE Industry Applica- Madison, where he worked on the synchronized
tions Society (IAS). implementation of cascaded multilevel inverters and
reduced common-mode carrier-based and hysteresis control strategies for
multilevel inverters. From 2002 to 2003, he was a Project Engineer at the
D. Mahinda Vilathgamuwa (S90M93SM99) Defence Science and Technology Agency, Singapore, managing major defense
received the B.Sc. and Ph.D. degrees in electri- infrastructure projects and exploring new technology for intelligent defense
cal engineering from the University of Moratuwa, applications. Since 2003, he has been an Assistant Professor at Nanyang
Katubedda Moratuwa, Sri Lanka, and Cambridge Technological University, Singapore.
University, Cambridge, U.K., in 1985 and 1993,
respectively.
He joined the School of Electrical and Elec-
tronic Engineering, Nanyang Technological Univer-
sity, Singapore, in 1993, as a Lecturer, where he is
now an Associate Professor. His research interests
are power electronic converters, electrical drives, and
power quality. He has published more than 80 research papers in refereed
journals and conference proceedings.
Dr. Vilathgamuwa is the Co-Chairman of The Power Electronics and Drives
Systems Conference 2005 (PEDS05).