74FCT3807 Datasheet PDF
74FCT3807 Datasheet PDF
74FCT3807 Datasheet PDF
FEATURES: DESCRIPTION:
0.5 MICRON CMOS Technology The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS
Guaranteed low skew < 350ps (max.) technology. This low skew clock driver offers 1:10 fanout. The large fanout from
Very low duty cycle distortion < 350ps (max.) a single input reduces loading on the preceding driver and provides an efficient
High speed: propagation delay < 3ns (max.) clock distribution network. The FCT3807/A offers low capacitance inputs with
Very low CMOS power levels hysteresis for improved noise margins. Multiple power and grounds reduce
TTL compatible inputs and outputs noise. Typical applications are clock and signal distribution.
1:10 fanout
Maximum output rise and fall time < 1.5ns (max.)
Low input capacitance: 4.5pF typical
VCC = 3.3V 0.3V
Inputs can be driven from 3.3V or 5V components
Available in SSOP, SOIC, and QSOP packages
O1
IN 1 20 VCC
O2 GND 2 19 O10
O1 3 18 O9
O3 VCC 4 17 GND
O2 5 16 O8
O4 GND 6 15 VCC
O3 7 14 O7
O5 VCC 8 13 GND
IN O4 9 12 O6
O6 GND 10 11 O5
O7
SOIC/ SSOP/ QSOP
TOP VIEW
O8
O9
O 10
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IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
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IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
FCT3807 FCT3807A
Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 30pF 1.5 4.5 1.5 4 ns
tPHL f 67MHz
tR Output Rise Time (See figure 3) 1.5 1.5 ns
tF Output Fall Time 1.5 1.5 ns
tSK(O) Output skew: skew between outputs of 0.5 0.35 ns
same package (same transition)
tSK(P) Pulse skew: skew between opposite transitions 0.5 0.35 ns
of same output (|tPHL - tPLH|)
tSK(T) Package skew: skew between outputs of different 1 0.75 ns
packages at same power supply voltage,
temperature, package type and speed grade
FCT3807 FCT3807A
Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 4.8 1.5 4.3 ns
tPHL f 40MHz
tR Output Rise Time (See figure 4) 1.5 1.5 ns
tF Output Fall Time 1.5 1.5 ns
tSK(O) Output skew: skew between outputs of 0.5 0.35 ns
same package (same transition)
tSK(P) Pulse skew: skew between opposite transitions 0.5 0.35 ns
of same output (|tPHL - tPLH|)
tSK(T) Package skew: skew between outputs of different 1 0.75 ns
packages at same power supply voltage,
temperature, package type and speed grade
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
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IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
FCT3807 FCT3807A
Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 30pF 1.5 4.5 1.5 4 ns
tPHL f 67MHz
tR Output Rise Time (See figure 3) 1.5 1.5 ns
tF Output Fall Time 1.5 1.5 ns
tSK(O) Output skew: skew between outputs of 0.6 0.45 ns
same package (same transition)
tSK(P) Pulse skew: skew between opposite transitions 0.6 0.45 ns
of same output (|tPHL - tPLH|)
tSK(T) Package skew: skew between outputs of different 1 0.75 ns
packages at same power supply voltage,
temperature, package type and speed grade
FCT3807 FCT3807A
Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 4.8 1.5 4.3 ns
tPHL f 40MHz
tR Output Rise Time (See figure 4) 1.5 1.5 ns
tF Output Fall Time 1.5 1.5 ns
tSK(O) Output skew: skew between outputs of 0.6 0.45 ns
same package (same transition)
tSK(P) Pulse skew: skew between opposite transitions 0.6 0.45 ns
of same output (|tPHL - tPLH|)
tSK(T) Package skew: skew between outputs of different 1 0.75 ns
packages at same power supply voltage,
temperature, package type and speed grade
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
5
IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS
VCC V CC V CC
100
V IN V OUT V IN V OUT
Pulse Pulse
D.U.T. D.U.T.
Generator Generator
10pF 50 10pF
100
RT RT
220pF
V CC V CC
V IN V OUT V IN V OUT
Pulse Pulse
D.U.T. D.U.T.
Generator Generator
30pF 50pF
RT CL RT CL
6V
V CC
GND
500
ENABLE AND DISABLE TIME
Pulse
V IN V OUT
SWITCH POSITION
D.U.T.
Generator
Test Switch
50pF
RT 500 Disable LOW 6V
CL
Enable LOW
Disable HIGH GND
Enable HIGH
Figure 5. Enable and Disable Time Circuit DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
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IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
TEST WAVEFORMS
3V 3V
1.5V 1.5V
INPUT 0V
INPUT 0V t PLH1 t PH L1
t PLH t PHL V OH
1.5V
V OH V OL
2.0V OUTPUT 1
1.5V t SK(o) t SK(o) V OH
0.8V
OUTPUT V OL 1.5V
OUTPUT 2 VOL
tR tF t PLH2 t PHL2
3V
3V 1.5V
1.5V INPUT 0V
t PLH1 t PH L1
INPUT 0V V OH
t PLH t PH L 1.5V
V OH
PACKAGE 1 OUTPUT V OL
1.5V t SK(t) t SK(t) V OH
OUTPUT V OL
1.5V
t SK(p) = |t PHL - t PLH | PACKAGE 2 OUTPUT V OL
t PLH2 t PH L2
Package 1 and Package 2 are same device type and speed grade
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IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT74FCT XXXX X X
Device Type Package Temp. Range
SO Small Outline IC
SOG SOIC - Green
PY Shrink Small Outline IC
PYG SSOP - Green
Q Quarter-size Small Outline IC
QG QSOP - Green
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