2ED2184 (4) S06F (J)

2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode
Features Product summary
• Unique Infineon Thin-Film-Silicon on Insulator (SOI)-Technology VS_OFFSET = 650 V max
• Negative VS transient immunity of 100 V Io+pk / Io-pk (typ.) =+ 2.5 A/ - 2.5 A
• Floating channel designed for bootstrap operation VCC = 10 V to 20 V
• Operating voltages (VS node) upto + 650 V Delay Matching = 35 ns max.
• Maximum bootstrap voltage (VB node) of + 675 V Propogation Delay = 200 ns
• Integrated ultra-fast, low resistance bootstrap diode tON / tOFF (typ.) = 600 ns/ 200 ns
• Logic Operational up to –11 V on VS Pin
• Negative Voltage Tolerance on Inputs of –5 V
• Independent under voltage lockout for both channels
Packages
• Schmitt trigger inputs with hysteresis
• 3.3 V, 5 V and 15 V input logic compatible
• Maximum supply voltage of 25 V
• Dual package options of DSO-8 and DSO-14
• High and Low Voltage Pins Separated for Maximum Creepage and
Clearance (2ED21844S06J version)
• Separate logic and power ground with the 2ED21844S06J version DSO-8 DSO-14
• Shutdown input turns off both channels
• Interlocking function with internal 400 ns dead time and
programmable up to 5 us with external resistor (2ED21844S06J only)
• RoHS compliant

Potential applications
Driving IGBTs, enhancement mode N-Channel MOSFETs in various power electronic applications.
Typical Infineon recommendations are as below:
• Motor drives, general purpose inverters having TrenchStop™ IGBT6 or 600 V EasyPACK™ modules
• Refrigeration compressors, induction cookers, other major home appliances having RCD series IGBTs or
TRENCHSTOP™ family IGBTs or their equivalent power stages
• Battery operated small home appliances such as power tools, vaccum cleaners using low voltage
OptiMOS™ MOSFETs or their equivalent power stages
• Totem pole, half-bridge and full-bridge converters in offline AC-DC power supplies for industrial SMPS having
high voltage CoolMOS™ super junction MOSFETs or TRENCHSTOP™ H3 and WR5 IGBT series
• High power LED and HID lighting having CoolMOS™ super junction MOSFETs
• Electric vehicle (EV) charging stations and battery management systems
• Driving 650 V SiC MOSFETs in above applications

Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22

Ordering information
Standard pack
Base part number Package type Orderable part number
Form Quantity
2ED2184S06F DSO-8 Tape and Reel 2500 2ED2184S06FXUMA1
2ED21844S06J DSO -14 Tape and Reel 2500 2ED21844S06JXUMA1

Datasheet Please read the Important Notice and Warnings at the end of this document V 2.31
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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

Description
The 2ED2184(4)S06F(J) is a half-bridge high voltage, high speed power MOSFET and IGBT driver with
independent high and low side referenced output channels. Based on Infineon’s SOI-technology there is an
excellent ruggedness and noise immunity with capability to maintain operational logic at negative voltages of
up to - 11 VDC on VS pin (VCC = 15 V) on transient voltages. There are not any parasitic thyristor structures present
in the device, hence no parasitic latch up may occur at all temperature and voltage conditions. The logic input
is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse
current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive
an N-channel power MOSFET, SiC MOSFET or IGBT in the high side configuration, which operate up to 650 V.

Up to 650V Up to 650V

2ED21844S06J
2ED2184S06F
IN 1 IN 14

IN 1 IN VB 8 SD 2 SD VB 13

SD 2 SD HO 7 VSS 3 VSS HO 12
RDT
3 VS 6 4 DT VS 11
COM
VCC TO LOAD TO LOAD
5 COM 10
4 LO VCC 5
6 LO 9

VCC 7 VCC 8

*Bootstrap diode is monolithically integrated

This diagram shows electrical connections only. Please refer to our application notes and design tips for proper circuit board layout.
Figure 1 Typical application block diagram

Summary of feature comparison of the 2ED218x family:

Table 1
Drive Cross
Current conduction Ground
Part No. Package Input logic Deadtime tON / tOFF
Source / prevention pins
Sink logic
+ 2.5 A /
2ED2181S06F DSO – 8 COM
- 2.5 A
+ 2.5 A / HIN, LIN No None
VSS /
2ED21814S06J DSO – 14 - 2.5 A COM
+ 2.5 A /
2ED2182S06F DSO – 8 Internal 400 ns COM
- 2.5 A
HIN, LIN Yes 200 ns /
+ 2.5 A / Programmable VSS /
2ED21824S06J DSO – 14 200 ns
- 2.5 A 400 ns - 5000 ns COM
+ 2.5 A /
2ED2183S06F DSO – 8 Internal 400 ns COM
- 2.5 A
+ 2.5 A / HIN, LIN Yes
Programmable VSS /
2ED21834S06J DSO – 14 - 2.5 A 400 ns - 5000 ns COM
+ 2.5 A / 600 ns /
2ED2184S06F DSO – 8 Internal 400 ns COM
- 2.5 A 200 ns
+ 2.5 A / IN, SD Yes
Programmable VSS /
2ED21844S06J DSO – 14 - 2.5 A 400 ns - 5000 ns COM

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

1 Table of contents
Product summary ........................................................................................................................................................ 1
Product validation ....................................................................................................................................................... 1
Description…...……………………………………………………………………………………………………………..2
1 Table of contents ................................................................................................................... 3
2 Block diagram ........................................................................................................................ 4
3 Pin configuration and functionality .......................................................................................... 5
3.1 Pin configuration ..................................................................................................................................... 5
3.2 Pin functionality ...................................................................................................................................... 5
4 Electrical parameters ............................................................................................................. 6
4.1 Absolute maximum ratings ..................................................................................................................... 6
4.2 Recommended operating conditions ..................................................................................................... 6
4.3 Static electrical characteristics ............................................................................................................... 7
4.4 Dynamic electrical characteristics .......................................................................................................... 8
5 Application information and additional details .......................................................................... 9
5.1 IGBT / MOSFET gate drive ....................................................................................................................... 9
5.2 Switching and timing relationships ........................................................................................................ 9
5.3 Deadtime and matched propagation delays........................................................................................ 10
5.4 Input logic compatibility ....................................................................................................................... 11
5.5 Undervoltage lockout ........................................................................................................................... 12
5.6 Shutdown Input..................................................................................................................................... 13
5.7 Bootstrap diode..................................................................................................................................... 13
5.8 Calculating the bootstrap capacitance CBS........................................................................................... 14
5.9 Tolerant to negative tranisents on input pins ...................................................................................... 15
5.10 Negative voltage transient tolerance of VS pin .................................................................................... 16
5.11 NTSOA – Negative Transient Safe Operating Area ............................................................................... 17
5.12 Higher headroom for input to output signal transmission with logic operation upto -11 V .............. 18
5.13 Maximum switching frequency ............................................................................................................. 18
5.14 PCB layout tips ...................................................................................................................................... 19
6 Qualification information.......................................................................................................21
7 Related products...................................................................................................................21
8 Package details .....................................................................................................................22
9 Part marking information ......................................................................................................23
10 Additional documentation and resources.................................................................................24
10.1 Infineon online forum resources .......................................................................................................... 24
11 Revision history ....................................................................................................................25

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

2 Block diagram

8 VB
UV
DETECT
2ED2184S06F R
Pulse R Q 7 HO
Filter S

6 VS
IN 1
Pulse BS diode
Generator

DT 5 VCC
Deadtime VCC
VCC UV
DETECT
+5V
VSS/COM
Delay LEVEL 4 LO
SD 2 Match SHIFT

3 COM

13 VB
UV
DETECT
2ED21844S06J R
Pulse R Q 12 HO
Filter S

11 VS
IN 1
Pulse BS diode
Generator

7 VCC
DT VCC
DT 4 Deadtime VCC UV
DETECT
+5V
VSS/COM
Delay LEVEL 6 LO
SD 2 Match SHIFT

5 COM
VSS 3

Figure 2 Block diagrams

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

3 Pin configuration and functionality

3.1 Pin configuration

1 IN 14
1 IN VB 8
2 VB 13
SD
2 SD HO 7 3 VSS HO 12

3 COM VS 6 4 DT VS 11

4 LO VCC 5 5 COM 10

6 LO 9

7 VCC 8

8-Lead DSO-8 (150 mil) 14-Lead DSO-14 (150 mil)

2ED2184S06F 2ED21844S06J

Figure 3 2ED2184(4)S06F(J) pin assignments (top view)

3.2 Pin functionality

Table 2
Symbol Description
Logic inputs for high and low side gate driver output (HO and LO), in phase with
IN
HO
𝐒𝐃 Logic input for shutdown
VSS Logic ground ( 2ED21844S06J only)
DT Programmable dead-time, referenced to VSS.( 2ED21844S06J only)
COM Low-side gate drive return
LO Low-side driver output
VCC Low-side and logic supply voltage
VS High voltage floating supply return
HO High-side driver output
VB High-side gate drive floating supply

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

4 Electrical parameters
4.1 Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.

Table 3 Absolute maximum ratings

Symbol Definition Min. Max. Units
VB High-side floating well supply voltage (Note 1) VCC – 5 675
VS High-side floating well supply return voltage VCC – VBS– 5 650
VHO Floating gate drive output voltage VS – 0.5 VB + 0.5
VCC Low side supply voltage -1 25
VLO Low-side output voltage –0.5 VCC + 0.5 V
VIN Logic input voltage (HIN & LIN) -5/ (VSS – 5) VCC + 0.5
Vss Logic ground (2ED21844S06J only) VCC – 25 VCC + 0.5
Programmable dead time pin voltage
DT VSS – 5 VCC + 0.5
(2ED21844S06J only)
dVS/dt Allowable VS offset supply transient relative to COM — 50 V/ns
Package power dissipation 8-Lead DSO-8 — 0.625
PD W
@ TA +25ºC 14-Lead DSO-14 — 1
Thermal resistance, junction 8-Lead DSO-8 — 200
RthJA ºC/W
to ambient 14-Lead DSO-14 — 120
TJ Junction temperature — 150
TS Storage temperature -55 150 ºC
TL Lead temperature (soldering, 10 seconds) — 300

Note 1: In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins V CC and VB in case of
activated bootstrap diode.

4.2 Recommended operating conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with
supplies of (VCC – COM) = (VB – VS) = 15 V.

Table 4 Recommended operating conditions

Symbol Definition Min Max Units
VB Bootstrap voltage VS + 10 VS + 20
VBS High-side floating well supply voltage 10 20
VS High-side floating well supply offset voltage Note 2 650
VHO Floating gate drive output voltage VS VB
VCC Low-side supply voltage 10 20
VLO Low-side output voltage COM VCC V
VIN Logic input voltage(HIN & LIN) -4 / (VSS – 4) 5 / (VSS + 5)
Logic ground (2ED21844S06J only) with respect to
VSS -5 +5
COM
Programmable dead time pin voltage
DT VSS – 4 5
(2ED21844S06J only)
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 2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

TA Ambient temperature -40 125 ºC

Note 2: Logic operation for VS of – 10 V to +650 V. Logic state held for VS of -10 to –VBS.

4.3 Static electrical characteristics

(VCC– COM) = (VB – VS) = 15 V, VSS = COM and TA = 25 °C unless otherwise specified. The VIL, VIH and IIN parameters
are referenced to Vss / COM and are applicable to the respective input leads: HIN and LIN. The V O and IO
parameters are referenced to VS / COM and are applicable to the respective output leads HO or LO. The VCCUV
parameters are referenced to COM. The VBSUV parameters are referenced to VS.

Table 5 Static electrical characteristics

Symbol Definition Min. Typ. Max. Units Test Conditions
VBS supply undervoltage positive going
VBSUV+ 7.6 8.2 8.9
threshold
VBS supply undervoltage negative going
VBSUV- 6.7 7.2 8.1
threshold
VBSUVHY VBS supply undervoltage hysteresis 1.0 — V
VCC supply undervoltage positive going
VCCUV+ 8.4 9.1 9.8
threshold
VCC supply undervoltage negative going
VCCUV- 7.5 8.2 8.9
threshold
VCCUVHY VCC supply undervoltage hysteresis 0.9 —
ILK High-side floating well offset supply leakage — 1 12.5 VB = VS = 650 V
IQBS Quiescent VBS supply current — 170 — uA All inputs are in
IQCC Quiescent VCC supply current — 550 — the off state
VOH High level output voltage drop, Vcc- VLO , VB- VHO — 0.05 0.2
V IO = 20 mA
VOL Low level output voltage drop, VO — 0.02 0.1
Io+mean Mean output current from 3 V to 6 V 1.65 2.2 CL = 22 nF
VO = 0 V
Io+ Peak output current turn-on1 2.5 —
PW ≤ 10 µs
A
Io-mean Mean output current from 12 V to 9 V 1.65 2.2 CL = 22 nF
VO = 15 V
Io- Peak output current turn-off1 2.5
PW ≤ 10 µs
VIH Logic “1” input voltage 1.7 2.1 2.4
VIL Logic “0” input voltage 0.7 0.9 1.1 V
Vcc=10 V to 20 V
VSD,TH+ SD Input positive going threshold 1.7 2.1 2.4
VSD,TH- SD Input negative going threshold 0.7 0.9 1.1
IIN+ Input bias current (Output = High) — 25 50 VIN = 5V, SD=0
µA
IIN- Input bias current (Output = Low) — — 10 VIN = 0V, SD=5V
Bootstrap diode forward voltage between Vcc
VFBSD — 1 1.2 V IF=0.3 mA
and VB
Bootstrap diode forward current between Vcc
IFBSD 55 100 145 mA VCC-VB=4 V
and VB
RBSD Bootstrap diode resistance 15 25 40 Ω VF1=4V,VF2=5 V
Allowable Negative VS pin voltage for IN
VS — -11 -10 V Vcc=15 V
Signal propagation to HO

1
Not subjected to production test, verified by characterization.

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 2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

4.4 Dynamic electrical characteristics

VCC = VBS= 15 V, VSS = COM, TA = 25 oC and CL = 1000 pF unless otherwise specified.

Table 6 Dynamic electrical characteristics

Symbol Definition Min. Typ. Max. Units Test Conditions
tON Turn-on propagation delay — 600 840
VS = 0 V or 650 V
tOFF Turn-off propagation delay — 200 300
tSD Shutdown propagation delay — 200 300
tR Turn-on rise time — 15 30 ns
VS = 0 V
tF Turn-off fall time — 15 30
Delay matching time (HS & LS turn-
MT — — 35
on/off)
Deadtime: LO Turn-off to HO Turn-on & 260 400 540 RDT=0 Ω
DT
HO Turn-off to LO turn-on 4 5 6 us RDT=200 kΩ
60 RDT=0 Ω
MDT Deadtime matching= I DTLO-HO – DTHO-LO I ns
600 RDT=200 kΩ

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

5 Application information and additional details

5.1 IGBT / MOSFET gate drive

The 2ED2184 (4) S06F (J) HVIC is designed to drive MOSFET or IGBT power devices. Figures 4 and 5 illustrate
several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC,
used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external
power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this
parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side
or low-side output voltage.

VB VB
(or VCC) (or VCC)

IO+
HO HO
(or LO) (or LO)
+
IO-
VHO (or VLO)
VS - VS
(or COM) (or COM)

Figure 4 HVIC Sourcing current Figure 5 HVIC Sinking current

5.2 Switching and timing relationships

The relationships between the input and output signals of the 2ED2184 (4) S06F (J) are illustrated below in
Figure 6 and Figure 7. From these figures, we can see the definitions of several timing parameters (i.e. tON, tOFF,
tR, and tF) associated with this device.

Figure 6 Switching timing diagram Figure 7 Input/output logic diagram

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

5.3 Deadtime and matched propagation delays

This 2ED2184 (4) S06F (J) features integrated deadtime protection circuitry. The deadtime is fixed for
2ED2184S06F; is programmable for 2ED2184S06J, it provides greater design flexibility. The deadtime feature
inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off;
this is done to ensure that the power switch being turned off has fully turned off before the second power
switch is turned on. This minimum deadtime is automatically inserter whenever the external deadtime is
shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 8 illustrates the
deadtime period and the relationship between the output gate signals.
The deadtime circuitry of 2ED2184 (4) S06F (J) is matched with respect to the high- and low-side outputs. Figure
9 defines the two deadtime parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT)
associated with the 2ED2184S06F (J) specifies the maximum difference between DTLO-HO and DTHO-LO.

Figure 8 Dead Time Definitions Figure 9 Delay Matching Waveform Definitions

The 2ED2184 (4) S06F (J) is designed with propagation delay matching circuitry. With this feature, the IC’s
response at the output to a signal at the input requires approximately the same time duration (i.e., t ON, tOFF) for
both the low-side channels and the high-side channels; the maximum difference is specified by the delay
matching parameter (MT). The propagation turn-on delay (tON) of the 2ED2184 (4) S06F (J) is matched to the
propagation turn-on delay (tOFF).
The 14-pin variant (2ED21844S06J) provides greater design flexibility with a programmable dead-time feature
using an external resistor (RDT) connected between the DT pin and VSS pin as shown in figure 10. A decoupling
ceramic capacitor (CDT > 1 nF) is recommended which is parallel with RDT.

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

Up to 650V

2ED21844S06J

IN 1 IN 14

SD 2 SD VB 13

VSS 3 VSS HO 12
RDT
4 DT VS 11
TO LOAD
CDT 5 COM 10

6 LO 9

VCC 7 VCC 8

Figure 10 14-pin half-bridge variants having adjustable dead-time feature settable with a resistor

Figure 11 shows the linear relationship between the resistor (RDT) and dead time. Based on the end
application, designers can choose to add the external resistor to increase the dead time. In case the DT pin is
left open, the gate driver enters protection mode switching off the output stages. Hence this pin has to be
connected to VSS pin with a 0 ohm to 200 k resistor based on application requirements. A 0 ohm (or shorted)
provides a minimum deadtime of 400 ns and 200 k ohm provides a maximum deadtime of 5 us.

Programmable dead time in

2ED21844S06J
6

5
Deadtime in us

0
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
External Resistor in kΩ

Figure 11 Variation of dead time vs. external resistor

5.4 Input logic compatibility

The input pins of are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc
supply voltage. With typical high threshold (VIH) of 2.1 V and typical low threshold (VIL) of 0.9 V, along with very
little temperature variation as summarized in Figure 12, the input pins are conveniently driven with logic level
PWM control signals derived from 3.3 V and 5 V digital power-controller devices. Wider hysteresis (typically
0.9 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the
hysteresis is typically less than 0.5 V. 2ED218x family also features tight control of the input pin threshold
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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

voltage levels which eases system design considerations and ensures stable operation across temperature. The
2ED218x features floating input protection wherein if any of the input pin is left floating, the output of the
corresponding stage is held in the low state. This is achieved using pull-down resistors on the input pin (IN) as
shown in the block diagram. The 2ED218x family has input pins that are capable of sustaining voltages higher
than the bias voltage applied on the Vcc pin of the device.

VIH

(IRS23364D)
Input Signal
VIL
Input Logic
Level

High

Low Low

Figure 12 IN input thresholds

5.5 Undervoltage lockout

This IC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply
and the VBS (high-side circuitry) power supply. Figure 13 is used to illustrate this concept; VCC (or VBS) is plotted
over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is
enabled or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC won’t turn-on. Additionally, if
the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition and shutdown the high and low-side gate drive outputs.
Upon power-up, should the VBS voltage fail to reach the VBSUV+ threshold, the IC won’t turn-on. Additionally, if
the VBS voltage decreases below the VBSUV- threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could
be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is
high; this could result in very high conduction losses within the power device and could lead to power device
failure.
VCC
(or VBS)

VCCUV+
VCCUV- (or VBSUV+)
(or VBSUV-)

Time

UVLO Protection
(Gate Drive Outputs Disabled)
Normal Normal
Operation Operation

Figure 13 UVLO protection

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

5.6 Shutdown Input

The 2ED2184S06F (J) is equipped with a shutdown (/SD) input pin that is used to shut down or enable the HVIC.
When the /SD pin is in the high state the HVIC is able to operate normally. When the /SD pin is in low state both
LO and HO are low.

Figure 14 Shutdown waveform definitions

5.7 Bootstrap diode

An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential
resistor of the diode helps to avoid extremely high inrush currents when initially charging the bootstrap
capacitor. The integrated diode with its resistrance helps save cost and improve reliability by reducing external
components as shown below figures 15 and 16.

Figure 15 2ED218x with integrated components Figure 16 Standard bootstrap gate driver

The low ohmic current limiting resistor provides essential advantages over other competitor devices with high
ohmic bootstrap structures. A low ohmic resistor such as in the 2ED218x family allows faster recharching of the
bootstrap capacitor during periods of small duty cycles on the low side transistor. Such points of operation
occur e.g. during low speed operation of drives at high torque, which can be excellently controlled with field-
oriented control of induction, permanent magnet synchronous or BLDC motors. There is usually no complete
recharging possible any more during small duty cycles, so that the bootstrap voltage at the bootstrap capacitor
CBS sinks. The bootstrap diode is usable for all kind power electronic converters. The bootstrap diode is a real
pn-diode and is temperature robust. It can be used at high temperatures with a low duty cycle of the low side
transistor.

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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

The bootstrap diode of the 2ED218x family works with all control algorithms of modern power electronics, such
as trapezoidal or sinusoidal drives control.

5.8 Calculating the bootstrap capacitance CBS

Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this
technique a supply voltage for the floating high side sections of the gate drive can be easily established
according to Figure 17.

Figure 17 Half bridge bootstrap circuit in 2ED218x

When the low side MOSFET turns on, it will force the potential of pin VS to GND. The existing difference between
the voltage of the bootstrap capacitor VCBS and VCC results in a charging current IBS into the capacitor CBS. The
current IBS is a pulse current and therefore the ESR of the capacitor C BS must be very small in order to avoid
losses in the capacitor that result in lower lifetime of the capacitor. This pin is on high potential again after low
side is turned off and high side is conducting current. But now the bootstrap diode D BS blocks a reverse current,
so that the charges on the capacitor cannot flow back to the capacitor CVCC. The bootstrap diode DBS also takes
over the blocking voltage between pin VB and VCC. The voltage of the bootstrap capacitor can now supply the
high side gate drive sections. It is a general design rule for the location of bootstrap capacitors CBS, that they
must be placed as close as possible to the IC. Otherwise, parasitic resistors and inductances may lead to
voltage spikes, which may trigger the undervoltage lockout threshold of the individual high side driver section.
The current limiting resistor RBS according to Figure 17 reduces the peak of the pulse current during the low side
MOSFET turn-on. The pulse current will occur at each turn-on of the low side MOSFET, so that with increasing
switching frequency the capacitor CBS is charged more frequently. Therefore a smaller capacitor is suitable at
higher switching frequencies. The bootstrap capacitor is mainly discharged by two effects: The high side
quiescent current and the gate charge of the high side MOSFET to be turned on.
The minimum size of the bootstrap capacitor is given by
𝑄𝐺𝑇𝑂𝑇
𝐶𝐵𝑆 =
∆𝑉𝐵𝑆
VBS is the maximum allowable voltage drop at the bootstrap capacitor within a switching period, typically 1 V.
It is recommended to keep the voltage drop below the undervoltage lockout (UVLO) of the high side and limit

VBS ≤ (VCC – VF– VGSmin– VDSon)

VGSmin > VBSUV- , VGSmin is the minimum gate source voltage we want to maintain and VBSUV- is the high-side supply
undervoltage negative threshold.
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2ED2184 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

VCC is the IC voltage supply, VF is bootstrapdiode forward voltage and VDSon is drain-source voltage of low side
MOSFET.
Please note, that the value QGTOT may vary to a maximum value based on different factors as explained below
and the capacitor shows voltage dependent derating behavior of its capacitance.
The influencing factors contributing VBS to decrease are:
- MOSFET turn on required Gate charge (QG)
- MOSFET gate-source leakage current (ILK_GS)
- Floating section quiescent current (IQBS)
- Floating section leakage current (ILK)
- Bootstrap diode leakage current (ILK_DIODE)
- Charge required by the internal level shifters (𝑄𝐿𝑆 ): typical 1nC
- Bootstrap capacitor leakage current (ILK_CAP)
- High side on time (THON)

Considering the above,

𝑄𝐺𝑇𝑂𝑇 = 𝑄𝐺 + 𝑄𝐿𝑆 + (𝐼𝑄𝐵𝑆 + 𝐼𝐿𝐾𝐺𝑆 + 𝐼𝐿𝐾 + 𝐼𝐿𝐾𝐷𝐼𝑂𝐷𝐸 + 𝐼𝐿𝐾𝐶𝐴𝑃 ) ∗ 𝑇𝐻𝑂𝑁

ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are
used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic capacitor
and low ESR ceramic capacitor may result in an efficient solution).
The above CBS equation is valid for pulse by pulse considerations. It is easy to see, that higher capacitance
values are needed, when operating continuously at small duty cycles of low side. The recommended bootstrap
capacitance is therefore in the range up to 4.7 μF for most switching frequencies. The performance of the
integrated bootstrap diode supports the requirement for small bootstrap capacitances.

5.9 Tolerant to negative tranisents on input pins

Typically the driver's ground pin is connected close to the source pin of the MOSFET or IGBT. The
microcontroller which sends the HIN and LIN PWM signals refers to the same ground and, in most cases, there
will be an offset voltage between the microcontroller ground pin and driver ground because of ground bounce.
The 2ED218x family can handle negative voltage spikes up to 5 V. The recommended operating level is at
negative 4 V with absolute maximum of negative 5 V. Standard half bridge or high-side/low-side drivers only
allow negative voltage levels down to -0.3 V. The 2ED218x family has much better noise immunity capability on
the input pins.

Figure 18 Negative voltage tolerance on inputs of upto –5 V

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5.10 Negative voltage transient tolerance of VS pin

A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase
inverter circuit is shown in Figure 19, here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 20 and 21) switches from on to off, while the U phase current
is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in
parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings
from the positive DC bus voltage to the negative DC bus voltage.

DC+ BUS

D1 Q3 D3 D5
Q1 Q5

W
V VS3 To
Input U VS2
Voltage VS1 Load

Q2 D2 Q4 D4 D6
Q6

DC- BUS

Figure 19 Three phase inverter

Also, when the V phase current flows from the inductive load back to the inverter (see Figures 20 C) and D)), and
Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node,
VS2, swings from the positive DC bus voltage to the negative DC bus voltage.
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather
it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”

DC+ BUS DC+ BUS DC+ BUS DC+ BUS

D1 D3 D3
Q1 Q1 Q3 Q3
ON OFF OFF OFF

IU IV
VS1 VS1 VS2 VS2
IU IV

D2 D2 D4
Q2 Q2 Q4 Q4
OFF OFF OFF ON

DC- BUS
A) DC- BUS
B) DC- BUS
C)
DC- BUS
D)
Figure 20 A) Q1 conducting B) D2 conducting C) D3 conducting D) Q4 conducting

The circuit shown in Figure 21-A depicts one leg of the three phase inverter; Figures 21-B and 21-C show a
simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the
power circuit from the die bonding to the PCB tracks are lumped together in L C and LE for each IGBT. When the
high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and
the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily
flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in
these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load
and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher
potential than the VS pin).
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DC+ BUS DC+ BUS DC+ BUS

+
LC1 VLC1
-

Q1 D1 D1
Q1 Q1
ON OFF

LE1 +
VLE1 IU
VS1 - VS1
VS1 -
LC2 VLC2 IU
+

Q2 D2 D2 -
Q2 Q2
VD2
OFF OFF +

-
LE2 VLE2
+
DC- BUS
A DC- BUS
B DC- BUS
C
Figure 21 Figure A shows the Parasitic Elements. Figure B shows the generation of VS positive. Figure C shows the
generation of VS negative

5.11 NTSOA – Negative Transient Safe Operating Area

In a typical motor drive system, dV/dt is typically designed to be in the range of 3 – 5 V / ns. The negative VS
transient voltage can exceed this range during some events such as short circuit and over-current shutdown,
when di/dt is greater than in normal operation.
Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications.
An indication of the 2ED2184’s robustness can be seen in Figure 22, where the 2ED2184’s Safe Operating Area is
shown at VBS=15 V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area
(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent
damage to the IC do not appear if negative Vs transients fall inside the SOA.

Recommended safe operating area

Figure 22 Negative VS transient SOA for 2ED2184(4)S06F(J) @ VBS=15 V

Even though the 2ED2184S06F(J) has been shown able to handle these large negative VS transient conditions, it
is highly recommended that the circuit designer always limit the negative VS transients as much as possible by
careful PCB layout and component use.

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5.12 Higher headroom for input to output signal transmission with logic
operation upto -11 V
If there is not enough voltage for the level shifter to transmit a valid signal to the high side.High side driver
doesn’t turn on. The level shifter circuit is with respect to COM (refer to Block Diagram on page 4), the voltage
from VB to COM is the supply voltage of level shifter. Under the condition of VS is negative voltage with respect
to COM, the voltage of VS - COM is decreased, as shown in Figure 21. There is a minimum operational supply
voltage of level shifter, if the supply voltage of level shifter is too low, the level shifter cannot pass through HIN
signal to HO. The specification of VS is –11 V as the internal structure allows a maximum voltage difference of 20
V between VB and VS pins. If VB – VS voltage is different, the minimum VS voltage changes accordingly.

VS

COM
- 11 V
Figure 23 Headroom for HV level shifter data transmission

5.13 Maximum switching frequency

The 2ED218x family is capable of switching at higher frequencies as compared to standard half-bridge or high
side / low side gate drivers. They are available in two packages, the PG-DSO-8 and the PG-DSO-14. It is essential
to ensure that the component is not thermally overloaded when operating at higher frequencies. This can be
checked by means of the thermal resistance junction to ambient and the calculation or measurement of the
dissipated power. The thermal resistance is given in the datasheet (section 4) and refers to a specific layout.
Changes of this layout may lead to an increased thermal resistance, which will reduce the total dissipated
power of the driver IC. One should therefore do temperature measurements in order to avoid thermal overload
under application relevant conditions of ambient temperature and housing.
The maximum chip temperature TJ can be calculated with
𝑇𝐽 = Pd ∙ 𝑅𝑡ℎ𝐽𝐴 + 𝑇𝐴_𝑚𝑎𝑥 , where TA_max is the maximum ambient temperature.

The dissipated power Pd by the driver IC is a combination of several sources. These are explained in detail in
the application note “Advantages of Infineon’s Silicon on Insulator (SOI) technology based High Voltage Gate
Driver ICs (HVICs)”
The output section is the major contributor for the power dissipation of the gate driver IC. The external gate
resistors also contribute to the power disspation of the gate driver IC. The bigger the external gate resistor, the
smaller the power dissipation in the gate driver.
The losses of the output section are calculated by means of the total gate charge of the power MOSFET or IGBT
it is driving Qgtot, the supply voltage VCC, the switching frequency fP, and the ext. gate resistor Rgon and Rgoff.
Different cases for turn-on and turn-off must be considered, because many designs use different resistors for
turn-on and turn-off. This leads to a specific distribution of losses in respect to the external gate resistor Rgxx, ext
and the internal resistances (Ron_int and Roff_int) of the output section.

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2 𝑅𝑜𝑛_𝑖𝑛𝑡
Turn on losses: 𝑃𝑑𝑜𝑛 = 2 × 𝑄𝑔𝑡𝑜𝑡 × 𝑉𝑐𝑐 × 𝑓𝑝 × 𝑅𝑜𝑛_𝑖𝑛𝑡+𝑅𝑔𝑜𝑛_𝑒𝑥𝑡

2 𝑅𝑜𝑓𝑓_𝑖𝑛𝑡
Turn off losses: 𝑃𝑑𝑜𝑓𝑓 = 2 × 𝑄𝑔𝑡𝑜𝑡 × 𝑉𝑐𝑐 × 𝑓𝑝 × 𝑅𝑜𝑓𝑓_𝑖𝑛𝑡+𝑅𝑔𝑜𝑓𝑓_𝑒𝑥𝑡

The above two losses are then added to the remaining static losses within the gate driver IC and we arrive at
the below figure which estimates the gate driver IC temperature rise when switching a given MOSFET or IGBT at
different switching frequencies.

*Assumptions for above curves: Ta = 25 °C, VBUS = 400 V, VCC = 12 V, Rgon = 10 Ω, Rgoff = 5Ω

Figure 24 Estimated temperature rise in the 2ED218x family gate drivers for different switching
frequencies when switching CoolMOSTM SJ MOSFETs

5.14 PCB layout tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied
to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the
Case Outline information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the
high voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
25). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive
loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the
IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to
developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.

Figure 25 Avoid antenna loops

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Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic
1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible
to the pins in order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage
transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to
avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance,
and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes
remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less)
between the VS pin and the switch node (see Figure 26), and in some cases using a clamping diode between
COM and VS (see Figure 27). See DT04-4 at www.infineon.com for more detailed explanations.

Figure 26 Resistor between the VS pin and Figure 27 Clamping diode between COM and VS
the switch node

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6 Qualification information1
Table 7 Qualification information
Industrial2
Note: This family of ICs has passed JEDEC’s Industrial
Qualification level
qualification. Consumer qualification level is granted by
extension of the higher Industrial level.
MSL2, 260°C
DSO-8
(per IPC/JEDEC J-STD-020)
Moisture sensitivity level
MSL33, 260°C
DSO-14
(per IPC/JEDEC J-STD-020)
Class C3 (1.0 kV)
Charged device model
(per JEDEC standard JS-002)
ESD
Class 2 (2 kV)
Human body model
(per JEDEC standard JS-001)
Class II Level A
IC latch-up test
(per JESD78)
RoHS compliant Yes

7 Related products
Table 8
Product Description
Gate Driver ICs
6EDL04I06 / 600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low RDS(ON) bootstrap
6EDL04N06 diodes with over-current protection (OCP), 240/420 mA source/sink current drive, Fault reporting,
and Enable for MOSFET or IGBT switches.
2EDL23I06 / 600 V, Half-bridge thin-film SOI level shift gate driver with integrated high speed, low
2EDL23N06 RDSON bootstrap diode, with over-current protection (OCP), 2.3/2.8 A source/sink current driver,
and one pin Enable/Fault function for MOSFET or IGBT switches.
Power Switches
IKD04N60R / RF 600 V TRENCHSTOP™ IGBT with integrated diode in PG-TO252-3 package
IKD06N65ET6 650 V TRENCHSTOP™ IGBT with integrated diode in DPAK
IPD65R950CFD 650 V CoolMOS CFD2 with integrated fast body diode in DPAK
IPN50R950CE 500 V CoolMOS CE Superjunction MOSFET in PG-SOT223 package
iMOTION™ Controllers
IRMCK099 iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented Control
(FOC) for Permanent Magnet Synchronous Motors (PMSM).
IMC101T High performance Motor Control IC for variable speed drives based on field oriented control (FOC)
of permanent magnet synchronous motors (PMSM).

1
Qualification standards can be found at Infineon’s web site www.infineon.com
2
Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales
representative for further information.
3
DSO-14 package with MSL2 rating is available if required. Please contact your Infineon sales representative for further information.
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8 Package details

Figure 28 8 - Lead DSO (2ED2184S06F)

Figure 29 14- Lead DSO (2ED21844S06J)

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9 Part marking information

Front Side Back Side

Part number 2ED2184 XXX

Infineon logo Lot code XXXX
Assembly
H YYWW Date code XXXX X site code
Pin 1
identifier
(may vary)

Figure 30 Marking information PG-DSO-8

Front Side

Infineon logo 2D21844S06J Part number

Date code Assembly

H YYWW XXX
site code

Pin 1 XXXXXXXXXXX Lot code

identifier

Figure 31 Marking information PG-DSO-14

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10 Additional documentation and resources

Several technical documents related to the use of HVICs are available at www.infineon.com; use the Site Search
function and the document number to quickly locate them. Below is a short list of some of these documents.

Application Notes:
Understanding HVIC Datasheet Specifications
HV Floating MOS-Gate Driver ICs
Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs
Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

Design Tips:
Using Monolithic High Voltage Gate Drivers
Alleviating High Side Latch on Problem at Power Up
Keeping the Bootstrap Capacitor Charged in Buck Converters
Managing Transients in Control IC Driven Power Stages
Simple High Side Drive Provides Fast Switching and Continuous On-Time

10.1 Infineon online forum resources

The Gate Driver Forum is live at Infineon Forums (www.infineonforums.com). This online forum is where the
Infineon gate driver IC community comes to the assistance of our customers to provide technical guidance –
how to use gate drivers ICs, existing and new gate driver information, application information, availability of
demo boards, online training materials for over 500 gate driver ICs. The Gate Driver Forum also serves as a
repository of FAQs where the user can review solutions to common or specific issues faced in similar
applications.

Register online at the Gate Driver Forum and learn the nuances of efficiently driving a power switch in any given
power electronic application.

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11 Revision history

Document Date of release Description of changes

version
2.00 July 30, 2019 Final Datasheet
2.10 September 12, 2019 Revised parameter values in Tables 5, 6 & 7 to match the test conditions.
Updated figure 1 to include 14 pin variant typical connection diagram.
2.20 January 14, 2020 Revised parameter values in Table 7 to match the test conditions. Added
deadtime settings section in page 10-11, revised DSO 14-pin package
marking information
2.21 July 07, 2020 IC latch-up test per JESD78
2.30 June 1, 2021 Corrected typo in Table 6, page 8. MT specifications and added the
recommended CDT capacitor on deadtime pin as shown in figure 10.
Updated block diagrams in figure 2.
2.31 Oct. 11, 2021 Merge V2.21 and V2.30.
Added interlocking function under Features section on page 1.

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