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    Lab 1 & 2

    Uploaded by

    Hisham Bin Tabassum
    This document provides instructions for two labs on FPGA system design. Lab 1 asks students to write Verilog code for a half adder using gate level, data flow, and behavioral modeling. Students are to synthesize and implement the code using Xilinx tools and attach the RTL schematics. Lab 2 instructs students to write code for blinking LEDs on an FPGA board and upload the program by following the specified procedure, attaching snapshots of each step. Sample half adder code is provided using gate level, data flow, and behavioral modeling.

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    Lab 1 & 2

    Uploaded by

    Hisham Bin Tabassum
    20 views4 pages
    This document provides instructions for two labs on FPGA system design. Lab 1 asks students to write Verilog code for a half adder using gate level, data flow, and behavioral modeling. Students are to synthesize and implement the code using Xilinx tools and attach the RTL schematics. Lab 2 instructs students to write code for blinking LEDs on an FPGA board and upload the program by following the specified procedure, attaching snapshots of each step. Sample half adder code is provided using gate level, data flow, and behavioral modeling.

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    This document provides instructions for two labs on FPGA system design. Lab 1 asks students to write Verilog code for a half adder using gate level, data flow, and behavioral modeling. Students are to synthesize and implement the code using Xilinx tools and attach the RTL schematics. Lab 2 instructs students to write code for blinking LEDs on an FPGA board and upload the program by following the specified procedure, attaching snapshots of each step. Sample half adder code is provided using gate level, data flow, and behavioral modeling.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    20 views4 pages

    Lab 1 & 2

    Uploaded by

    Hisham Bin Tabassum
    This document provides instructions for two labs on FPGA system design. Lab 1 asks students to write Verilog code for a half adder using gate level, data flow, and behavioral modeling. Students are to synthesize and implement the code using Xilinx tools and attach the RTL schematics. Lab 2 instructs students to write code for blinking LEDs on an FPGA board and upload the program by following the specified procedure, attaching snapshots of each step. Sample half adder code is provided using gate level, data flow, and behavioral modeling.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    FPGA BASED SYSTEM DESIGN LAB

    LAB 1 & 2 TASK

    LAB 1:
    1. Write Verilog HDL code for Half Adder using Gate Level, Data Flow and Behavioural
    Modeling.
    Synthesize and implement using Xilinx tools and also attach RTL schematic of each modeling
    repectively.

    SOLUTION:
    CODE:
    module adder( a,b,sum,cout);

    input a;

    input b;

    output sum;

    output cout;

    xor(sum,a,b);

    and(cout,a,b);

    endmodule

    DATA FLOW:

    module adder( a,b,sum,cout);

    input a;

    input b;

    output sum;

    output cout;

    assign sum = a^b;

    assign cout = a&b;

    endmodule;
    BEHAVIOURAL:

    module adder( a,b,sum,cout);

    input a;

    input b;

    output sum;

    output cout;

    reg sum;

    reg cout;

    always@(a or b)

    begin

    sum = a^b;

    cout = a&b;

    end

    endmodule

    IMPLEMENTATION:
    LAB 2:
    Write a Verilog code for blinking LEDs on FPGA board. Upload the program on board by
    following the above procedure. Attach snapshots of each step.
    SOLUTION/IMPLEMENTATION:

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