74123-9601-9602 Aplicaciones PDF
74123-9601-9602 Aplicaciones PDF
74123-9601-9602 Aplicaciones PDF
National Semiconductor
Designers Encyclopedia of Application Note 366
One-Shots Kern Wong
July 1984
INTRODUCTION
National Semiconductor manufactures a broad variety of in- Nearly all malfunctions and failures on one-shots are
dustrial bipolar monostable multivibrators (one-shots) in TTL caused by misuse or misunderstanding of their fundamental
and LS-TTL technologies and MOS one-shots in CMOS and operating rules, characteristic design equations, parame-
HCMOS technologies to meet the stringent needs of sys- ters, or more frequently by poor circuit layout, improper by-
tems designers for applications in the areas of pulse gener- passing, and improper triggering signal.
ation, pulse shaping, time delay, demodulation, and edge In the following sections all one-shots (bipolar and MOS)
detection of waveforms. Features of the various device manufactured by National Semiconductor are presented
types include single and dual monostable parts, retriggera- with features tables and design charts for comparisons. Op-
ble and non-retriggerable devices, direct clearing input, and erating rules are outlined for devices in general and for spe-
DC or pulse-triggered inputs. Furthermore, to provide the cific device types. Notes on unique differences per device
designer with complete flexibility in controlling the pulse and on special operating considerations are detailed. Final-
width, some devices also have Schmitt trigger input, and/or ly, truth tables and connection diagrams are included for
contain internal timing components for added design conve- reference.
nience.
For completeness, reference of an ECL monostable multivi-
DESCRIPTION brator is included in this note. Also included is a PC layout of
One-shots are versatile devices in digital circuit design. a one-shot AC test adapter board and typical one-shot ap-
They are actually quite easy to use and are best suited for plications.
applications to generate or to modify short timings ranging DEFINITION
from several tens of nanoseconds to a few microseconds.
A one-shot integrated circuit is a device that, when trig-
However, difficulties are constantly being experienced by
gered, produces an output pulse width that is independent
design and test engineers, and basically fall into the catego-
of the input pulse width, and can be programmed by an
ries of either pulse width problems or triggering difficulties.
external Resistor-Capacitor network. The output pulse width
The purpose of this note is to present an overall view of will be a function of the RC time constant. There are various
what one-shots are, how they work, and how to use them one-shots manufactured by National Semiconductor that
properly. It is intended to give the reader comprehensive have diverse features, although, all one-shots have the ba-
information which will serve as a designers guide to one- sic property of producing a prorammable output pulse width.
shots. All National one-shots have True and Complementary out-
puts, and both positive and negative edge-triggered inputs.
TTL AND LS-TTL ONE-SHOT FEATURES
DM9602 DM74121
Timing equations listed in the features
tables hold for all combinations of
REXT and CEXT for all cases of
CEXT l 1000 pF. For cases where the
CEXT k 1000 pF, use the graphs
shown below.
TL/F/6738 1
TL/F/6738 2
DM74121 DM9602
The graphs shown below demonstrate
the typical shift in the device output
pulse widths as a function of tempera-
ture. It should be noted that these
graphs represent the temperature shift
of the device after being corrected for
any temperature shift in the timing
components. Any shift in these com-
ponents will result in a corresponding
shift in the pulse width, as well as any
shift due to the device itself.
TL/F/6738 3
2
Typical Output Pulse Width Variation vs Ambient Temperature (Continued)
74LS221 DM74LS123 DM74123
TL/F/6738 4
DM9602 DM74121
The following graphs show the depen-
dence of the pulse width on VCC.
As with any IC applications, the device
should be properly bypassed so that
large transient switching currents can
be easily supplied by the bypass ca-
pacitor. Capacitor values of 0.001 mF
to 0.10 mF are generally used for the
VCC bypass capacitor.
TL/F/6738 5
TL/F/6738 6
3
Typical K Coefficient Variation vs Timing Capacitance
DM9602 DM74121
For certain one-shots, the K coeffi-
cient is not a constant, but varies as a
function of the timing capacitor CEXT.
The graphs below detail this charac-
teristic.
TL/F/6738 7
TL/F/6738 8
DM9602 DM74121
The plots shown below demonstrate
typical pulse widths and limiting values
of the true output as a function of the
external timing resistor, REXT. This in-
formation should evaporate those
years of mysterious notions and nu-
merous concerns about operating
one-shots with lower than recom-
mended minimum REXT values.
TL/F/6738 9
4
Typical Output Pulse Width vs Minimum Timing Resistance (Continued)
DM74123 DM74LS123 DM74LS221
TL/F/6738 10
Inputs Outputs
TL/F/6738 11
Clear A1 A2 B1 B2 Q Q Top View
L X X X X L H
X H H X X L H 54LS122 (J, W); 74LS122 (N)
X X X L X L H
X X X X L L H
X L X H H L H
H L X u H
H L X H u
H X L H H L H
H X L u H
H X L H u
H H v H H
H v v H H
H v H H H
u L X H H
u X L H H
H e HIGH Level
L e LOW Level
u e Transition from LOW-to-HIGH
v e Transition from HIGH-to-LOW TL/F/6738 12
e One HIGH Level Pulse Top View
e One LOW Level Pulse
X e Dont Care
5
Truth Tables (Continued) Connection Diagrams (Continued)
123 Dual Retriggerable One-Shots with Clear 54123 (J, W); 74123 (N),
54L123A (J, W); 74L123A (N)
123, L123A
Inputs Outputs
A B CLR Q Q
H X H L H
X L H L H
L u H
v H H
X X L L H
TL/F/6738 13
Top View
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H
H L u
H v H
u L H
TL/F/6738 14
Top View
8602
Pin Numbers
Operation
A B CLR
HxL L H Trigger
H LxH H Trigger
X X L Reset
H e HIGH Level
L e LOW Level
u e Transition from LOW-to-HIGH
v e Transition from HIGH-to-LOW
e One HIGH Level Pulse
e One LOW Level Pulse
X e Dont Care
TL/F/6738 15
Top View
6
Truth Tables (Continued) Connection Diagrams (Continued)
8853 Triggering Truth Table 7853 (J, W); 8853 (N)
t Dt CD Operation
LxH L H Trigger
H HxL H Trigger
HxL H H Trigger
L LxH H Trigger
HxL Same as t H Trigger
LxH Same as t H Trigger
X X L Reset
221 Dual One-Shots with Schmitt Trigger Inputs 54LS221 (J, W); 74LS221 (N)
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H
H L u
H v H
u L H
TL/F/6738 17
Inputs Outputs
A1 A2 B1 B2 Q Q 9601 (J, W); 8601 (N)
H H X X L H
X X L X L H
X X X L L H
L X H H L H
L X u H
L X H u
X L H H L H
X L u H
X L H u
H v H H
v v H H
v H H H
H e HIGH Level
L e LOW Level
u e Transition from LOW-to-HIGH
v e Transition from HIGH-to-LOW
e One HIGH Level Pulse
TL/F/6738 18
e One LOW Level Pulse
X e Dont Care Top View
7
CMOS AND HCMOS ONE-SHOT FEATURES
MM14538
MM74HC221 CD4538 MM74HC4538
TL/F/6738 19
8
Truth Tables (Continued) Connection Diagrams (Continued)
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H
H L u
H v H
u L H
TL/F/6738 20
Top View
Timing Component
MM54HC423/MM74HC423
54HC423 (J); 74HC423 (J, N)
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H
TL/F/6738 21
H L u
H v H
MM54HC4538/MM74HC4538
54HC4538 (J); 74HC4538 (J, N)
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H
H L v
H u H
H e HIGH Level
L e LOW Level TL/F/6738 22
u e Transition from LOW-to-HIGH Top View
v e Transition from HIGH-to-LOW
e One HIGH Level Pulse
e One LOW Level Pulse
X e Dont Care
9
Truth Tables (Continued) Connection Diagrams (Continued)
MM54C221
MM74C221
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H
H L u
H v H
H e HIGH Level
L e LOW Level
u e Transition from LOW-to-HIGH
v e Transition from HIGH-to-LOW
e One HIGH Level Pulse
e One LOW Level Pulse
X e Dont Care TL/F/6738 23
Top View
Timing Component
TL/F/6738 24
Block Diagrams
RX and CX Are External Timing Components
TL/F/6738 25
10
Typical Performance Characteristics
MM54/74HC123, HC423, HC221, HC4538
Typical K Coefficient
Minimum REXT vs Typical 1 ms Pulse Width Variation vs Supply Voltage
Supply Voltage Variation vs Temperature MM54/74 HC4538
TL/F/6738 26
Typical Output Pulse Width Typical Distribution of Output Typical 1 ms Pulse Width
vs Timing Components Pulse Width, Part to Part Variation vs Supply Voltage
TL/F/6738 27
MM54/74C221
TL/F/6738 29
TL/F/6738 28
11
MM54/74C221 (Continued)
Typical Performance Characteristics
TL/F/6738 31
TL/F/6738 30
CD4047BM/CD4047BC
Block and Connection Diagrams
TL/F/6738 32
TL/F/6738 33
Top View
12
CD4047 (Continued)
Truth Table
Terminal Connections Typical Output Period
Function Output Pulse From
To VDD To VSS Input Pulse To or Pulse Width
Astable Multivibrator
Free-Running 4, 5, 6, 14 7, 8, 9, 12 10, 11, 13
tA (10, 11) e 4.40 RC
True Gating 4, 6, 14 7, 8, 9, 12 5 10, 11, 13
tA (13) e 2.20 RC
Complement Gating 6, 14 5, 7, 8, 9, 12 4 10, 11, 13
Monostable Multivibrator
Positive Edge-Trigger 4, 14 5, 6, 7, 9, 12 8 10, 11
Negative Edge-Trigger 4, 8, 14 5, 7, 9, 12 6 10, 11 tM (10, 11) e 2.48 RC
Retriggerable 4, 14 5, 6, 7, 9 8, 12 10, 11
External Countdown* 14 5, 6, 7, 8, 9, 12 (See Figure *) (See Figure *) (See Figure *)
Note: External resistor between terminals 2 and 3; external capacitor between terminals 1 and 3.
TL/F/6738 34
Timing Diagrams
Astable Mode Monostable Mode
TL/F/6738 35
TL/F/6738 36
Retrigger Mode
TL/F/6738 37
13
CD4047 (Continued)
Typical Performance Characteristics
TL/F/6738 39
TL/F/673838
tM R C
fQ, Q R C
A 2 ms 22k 10 pF
A 1000 kHz 22k 10 pF
B 7 ms 22k 100 pF
B 100 kHz 22k 100 pF
C 60 ms 220k 100 pF
C 10 kHz 220k 100 pF
D 550 ms 220k 1000 pF
D 1 kHz 220k 1000 pF
E 5.5 ms 2.2M 1000 pF
E 100 Hz 2.2M 1000 pF
TL/F/6738 41
TL/F/673840
fQ, Q R C tM R C
A 1000 kHz 22k 10 pF A 2 ms 22k 10 pF
B 100 kHz 22k 100 pF B 7 ms 22k 100 pF
C 10 kHz 220k 100 pF C 60 ms 220k 100 pF
D 1 kHz 220k 1000 pF D 500 ms 220k 1000 pF
14
CD4528BM/CD4528BC
Block and Connection Diagrams
Dual-In-Line Package Dual-In-Line Package
TL/F/6738 42
Top View
Truth Table
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H TL/F/6738 43
H L v Top View
H u H
H e HIGH Level
L e LOW Level
u e Transition from LOW-to-HIGH
v e Transition from HIGH-to-LOW
e One HIGH Level Pulse
e One LOW Level Pulse
X e Dont Care
TL/F/6738 44
TL/F/6738 45
15
CD4538BM/CD4538BC Block Diagrams
Truth Table
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H
X X L L H
H L v
H u H
H e HIGH Level
L e LOW Level
u e Transition from LOW-to-HIGH
v e Transition from HIGH-to-LOW
e One HIGH Level Pulse
e One LOW Level Pulse
X e Dont Care
TL/F/6738 46
CD4538BM, CD4538BC
Typical Performance Characteristics
Typical Normalized Typical Pulse Width
Distribution of Units for Typical Pulse Width Error Variation as a Function
Output Pulse Width vs Temperature of Supply Voltage VDD
TL/F/6738 47
16
CD4538 (Continued)
Typical Performance Characteristics
Typical Total Supply
Current vs Output Duty
Cycle, RX e 100 kX,
CL e 50 pF, CX e 100 pF
Typical Pulse Width Error (One Monostable Typical Pulse Width vs
vs Temperature Switching Only) Timing RC Product
TL/F/6738 48
TL/F/6738 49
Truth Table
Inputs Output
EPos ENeg
L L Triggers on both positive and
negative input slopes
L H Triggers on positive input slope TL/F/6738 50
H L Triggers on negative input slope
H H Trigger is disabled
H e HIGH Level
L e LOW Level
17
Typical Performance Characteristics (Continued)
MC10198
Pulse Width vs
Temperature and Pulse Width vs
Supply Voltage IT @ CEXT e 13 pF
TL/F/673851 TL/F/6738 52
MC10198
TL/F/673853
TL/F/6738 54
Note: The MC10198 is made by Motorola and the DM74HC4538 is also a Motorola-designed part, which is a cooperative trade part of the HC one-shots between
NSC and Motorola. Information courtesy of Motorola Inc.
OPERATING RULES
In all cases, R and C represented by the timing equations will result in a voltage difference between the capacitor and
are the external resistor and capacitor, called REXT and the one-shot. Since the one-shot is designed to discharge
CEXT, respectively, in the data book. All the foregoing timing the capacitor to a specific fixed voltage, the series voltage
equations use C in pF, R in Kohms, and yield tW in nanosec- will fool the one-shot into releasing the capacitor before
onds. For those one-shots that are not retriggerable, there the capacitor is fully discharged. This will result in a pulse
is a duty cycle specification associated with them that de- width that appears much shorter than the programmed val-
fines the maximum trigger frequency as a function of the ue. We have encountered users who have been frustrated
external resistor, REXT. by pulse width problems and had difficulty performing correl-
In all cases, an external (or internal) timing resistor (REXT) ations with commercial test equipment. The nature of such
connects from VCC or another voltage source to the REXT/ problems are usually related to the improper layout of the
CEXT pin, and an external timing capacitor (CEXT) con- DUT adapter boards. (See Figure 6 for a PC layout of an AC
nects between the REXT/CEXT and CEXT pins are re- test adapter board.) It has been demonstrated that lead
quired for proper operation. There are no other elements length greater than 3 cm from the timing component to the
needed to program the output pulse width, though the value device pins can cause pulse width problems on some devic-
of the timing capacitor may vary from 0.0 to any necessary es.
value. For precise timing, precision resistors with good tempera-
When connecting the REXT and CEXT timing elements, care ture coefficients should be used. Similarly, the timing capac-
must be taken to put these components absolutely as close itor must have low leakage, good dielectric absorption char-
to the device pins as possible, electrically and physically. acteristic, and a low temperature coefficient for stability.
Any distance between the timing components and the de- Please consult manufacturers to obtain the proper type of
vice will cause time-out errors in the resulting pulse width, component for the application. For small time constants,
because the series impedance (both resistive and inductive)
18
high-grade mica glass, polystyrene, polypropylene, or poly-
carbonate capacitor may be used. For large time constants,
use a solid tantalum or special aluminum capacitor.
In general, if small timing capacitor has leakage approach-
ing 100 nA or if the stray capacitance from either terminal to
ground is greater than 50 pF, then the timing equations or TL/F/6738 57
design curves which predict the pulse width would not rep- FIGURE 3
resent the programmed pulse width which the device gener-
ates. tRET e tW a tPLH e K # (REXT)(CEXT) a tPHL
When an electrolytic capacitor is used for CEXT, a switching (See tables for exact expressions for K and tW; K is unity on
diode is often suggested for standard TTL one-shots to pre- most HCMOS devices.)
vent high inverse leakage current (Figure 1) . In general, this
SPECIAL CONSIDERATIONS AND NOTES:
switching diode is not required for LS-TTL, CMOS, and
HCMOS devices; it is also not recommended with retrigger- The 9601 is the single version of the dual 9602 one-shots,
able applications. and the 8853, except for the input gating networks, has ba-
sically the same circuit as the 9602. With the exception of
an internal timing resistor, Rint, the LS122 has performance
characteristics virtually identical to the LS123. Also, except
for the gating networks of the input sections, the timing cir-
cuitry of the HC123, HC221, HC423, and HC4538 are
identical, and their performance characteristics are essen-
tially the same. The design and characteristic curves for
equivalent devices are not depicted individually, as they can
TL/F/6738 55 be referenced from their parent device.
FIGURE 1 Nationals TTL-123 dual retriggerable one-shot features a
It is never a good practice to Ieave any unused inputs of a unique logic realization not implemented by other manufac-
logic integrated circuit floating. This is particularly true for turers. The CLEAR input does not trigger the device, a
one-shots. Floating uncommitted inputs or attempts to es- design tailored for applications where it is desired only to
tablish a logic HIGH level in this manner will result in mal- terminate or to reduce the timing pulse width.
function of some devices. The LS221, even though it has pin-outs identical to the
Operating one-shots with values of the REXT outside the LS123, is not functionally identical. It should be remem-
recommended limits is at the risk of the user. For some bered that the LS221 is a non-retriggerable one-shot, while
devices it will lead to complete inoperation, while for other the LS123 is a retriggerable one. For the LS123 device, it
devices it may result in either pulse widths different from is sometimes recommended to externally ground its CEXT
those values predicted by design charts or equations, or pin for improved system performance. The CEXT pin on
with modes of operation and performance quite different the LS221, however, is not an internal connection to the
from known standard characterizations. device ground. Hence, grounding this pin on the LS221 de-
To obtain variable pulse width by remote trimming, the fol- vice will render the device inoperative.
lowing circuit is recommended (Figure 2) . Remote should Furthermore, if a polarized timing capacitor is used on the
be placed as close to the one-shot as possible. LS221, the positive side of the capacitor should be con-
nected to the CEXT pin. For the LS123 part, it is the con-
trary, the negative terminal of the capacitor should be con-
nected to the CEXT pin of the device (Figure 4) .
TL/F/6738 56
FIGURE 2
VCC and ground wiring should conform to good high fre-
quency standards and practices so that switching transients
on the VCC and ground return leads do not cause interac-
tion between one-shots. A 0.001 mF to 0.1 mF bypass ca-
TL/F/6738 58
pacitor (disk or monolithic type) from the VCC pin to ground
FIGURE 4
is necessary on each device. Furthermore, the bypass ca-
pacitor should be located so as to provide as short an elec- The LS221 trigger on CLEAR: This mode of trigger re-
trical path as possible between the VCC and ground pins. In quires first the B-Input be set from a Low-to-High level
severe cases of supply-line noise, decoupling in the form of while the CLEAR input is maintained at logic Low level.
a local power supply voltage regulator is necessary. Then, with the B Input at logic High level, the CLEAR
For retriggerable devices the retrigger pulse width is calcu-
lated as follows for positive-edge triggering:
19
input, whose positive transition from LOW-to-HIGH will trig- The L123 low-power version of the TTL 123 one-shot is
ger an output pulse (A input is LOW). being deleted from the NSC product line.
AC Test Adapter Board
The compact PC layout below is a universal one-shot test
adapter board. By wiring different jumpers, it can be config-
ured to accept all one-shots made by National Semiconduc-
tor. The configuration shown below is dedicated for the 123
device. It has been used successfully for functional and
pulse width testing on all the 123 families of one-shots on
the Teradyne AC test system.
TL/F/673859
FIGURE 5
TL/F/673860
TL/F/6738 61
FIGURE 6a. AC Test Adapter
FIGURE 6b. AC Test Adapter
DM54LS123 One-Shot
TL/F/6738 62
FIGURE 7a. Timing Components and I/O Connections to D.U.T.
20
TL/F/6738 64
TL/F/6738 63
Note: Textool 16 Pin DUT socket, do not use sockets for K1, 2.
FIGURE 7b
Applications
The following circuits are shown with generalized one-shot
connection diagram.
TL/F/6738 65
FIGURE 8. Noise Discriminator
21
TL/F/6738 66
FIGURE 8. Noise Discriminator (Continued)
TL/F/6738 68
TL/F/673867
FIGURE 9. Frequency Discriminator
TL/F/6738 70
FIGURE 10b. Schmitt Trigger
TL/F/673869
TL/F/6738 71
FIGURE 10a. Envelope Detector (Retriggerable Device Required)
22
Pulse Generator (Figure 11)
Two one-shots can be connected together to form a pulse the frequency developed at output Q1. RX2 and CX2 of O-S2
generator capable of variable frequency and independent determine the output pulse width at Q2. (Retriggerable de-
duty cycle control. The RX1 and CX1 of O-S1 determine vice required.)
TL/F/6738 72
RX2 CX2
DUTY CYCLE e
RX1 CX1
1
FREQ e
K RX1 CX1
TL/F/6738 73
FIGURE 11. Pulse Generator (Retriggerable Device Required)
Note: K is the multiplication factor dependent of the device. Arrow indicates edge-trigger mode.
TL/F/6738 74
TL/F/6738 75
FIGURE 12. Delayed Pulse Generator with Override To Terminate Output Pulse
23
Missing Pulse Detector (Figure 13)
By setting the time constant of O-S1 through RX1 and CX1 is missing in the incoming pulse train, which then triggers O-
to be at least one full period of the incoming pulse period, S2 and produces an indicating pulse at Q2. (Retriggerable
the one-shot will be continuously retriggered as long as no device required.)
missing pulse occurs. Hence, Q1 remains LOW until a pulse
TL/F/6738 76
TL/F/6738 77
FIGURE 13. Missing Pulse Detector (Retriggerable Device Required)
TL/F/6738 78
FIGURE 14. Pulse Width Detector
24
TL/F/6738 79
FIGURE 14. Pulse Width Detector (Continued)
TL/F/6738 80
TL/F/6738 81
FIGURE 15. Band Pass Filter (Retriggerable Device Required)
25
FM Data Separator (Figure 16)
The data separator shown in Figure 16 is a two-time con- With O-S1 and O-S2 inactive, a CLK WINDOW is active.
stant separator that can be used on tape and disc drive The first a READ DATA pulse will be gated through the
memory storage systems. The clock and data pulses must second AND gate, which becomes bSEP CLK for triggering
fall within prespecified time windows. Both the clock and of the R-S FF and the one-shots. With the D-FF off, O-S1
data windows are generated in this circuit. There are two will remain reset. The bSEP CLK pulse will trigger O-S2,
data windows; the short window is used when the previous whose output is sent to the OR gate, and its output be-
bit cell had a data pulse in it, while the long window is used comes a DATA WINDOW to enable the first AND gate. The
when the previous bit cell had no data pulse. next pulse on a READ DATA will be allowed through the
If the data pulse initially falls into the data window, the first AND gate to become bSEP DATA. This pulse sets the
b SEP DATA output returns to the NAND gate that gener- R-S FF, whose HIGH output becomes the data to the D-FF.
ates the data window, to assure that the full data is allowed The D-FF is clocked on by O-S2 timing out and
through before the window times out. The clock windows a CLK WINDOW becoming active. Q4 will hold O-S2 reset
will take up the remainder of the bit cell time. and allow O-S1 to trigger on the next clock pulse.
Assume all one-shots and flip-flops are reset initially and the
a READ DATA has the data stream as indicated.
TL/F/6738 82
FIGURE 16. FM Data Separator
26
The next clock pulse (the second bit cell) is ANDed with setting the R-S FF and triggers O-S2. When O-S2 becomes
a CLK WINDOW and becomes the next b SEP CLK, which active, a DATA WINDOW enables the first AND gate, allow-
will reset the R-S FF and trigger O-S1. As O-S1 becomes ing the data pulse in bit cell 3 to become bSEP DATA. This
active, the a DATA WINDOW becomes active, enabling the b SEP DATA will set the R-S FF, which enables the D-FF to
first AND gate. With no data bit in the second bit cell, the be clocked on when a DATA WINDOW falls. When this
R-S FF will remain reset, enabling the D-FF to be clocked happens, Q4 will hold O-S2 reset and allow O-S1 to trigger.
off when a DATA WINDOW falls. When the D-FF is clocked This procedure continues as long as there is clock and data
off, Q4 will hold O-S1 reset and allow O-S2 to be triggered. pulse stream present on the a READ DATA line.
The third clock pulse (bit cell 3) is ANDed with a CLK
WINDOW and becomes bSEP CLK, which continues re-
TL/F/6738 83
FIGURE 16. FM Data Separator (Continued)
27
duces the positive control voltage at the VCO input in direct ing circuit be connected to the output of the op-amp to pre-
proportion to the duration of the phase-error pulse. A nega- vent the VCO control voltage from going negative or more
tive phase-error pulse occurs when the phase detector FF positive than necessary. A back-to-back diode pair connect-
remains set longer than the one-shot. ed between the op-amp and the VCO is highly recommend-
Negative phase-error pulse causes the integrated control ed, for it will present a high impedance to the VCO input
voltage to swing positive in direct proportion to the duration during locked mode. This way, stable and smooth operation
of the phase-error pulse. It is recommended that a clamp- of the PLO circuit is assured.
TL/F/6738 84
TL/F/6738 85
FIGURE 17. Phase-Locked Loop Voltage Controlled Oscillator
28
A FlNAL NOTE ACKNOWLEDGEMENT
It is hoped that this brief note will clarify many pertinent and The author wishes to thank Stephen Wong, Bill Llewellyn,
subtle points on the use and testing of one-shots. We invite Walt Sirovy, Dennis Worden, Stephen Yuen, Weber Lau,
your comments to this application note and solicit your con- Chris Henry and Michelle Fong for their help and guidance.
structive criticism to help us improve our service to you.
29
Designers Encyclopedia of One-Shots
NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.