National Semiconductor manufactures a broad variety of industrial bipolar monostable multivibrators (one-shots) in TTL
and LS-TTL technologies and MOS one-shots in CMOS and
HCMOS technologies to meet the stringent needs of systems designers for applications in the areas of pulse generation, pulse shaping, time delay, demodulation, and edge
detection of waveforms. Features of the various device
types include single and dual monostable parts, retriggerable and non-retriggerable devices, direct clearing input, and
DC or pulse-triggered inputs. Furthermore, to provide the
designer with complete flexibility in controlling the pulse
width, some devices also have Schmitt trigger input, and/or
contain internal timing components for added design convenience.
DESCRIPTION
One-shots are versatile devices in digital circuit design.
They are actually quite easy to use and are best suited for
applications to generate or to modify short timings ranging
from several tens of nanoseconds to a few microseconds.
However, difficulties are constantly being experienced by
design and test engineers, and basically fall into the categories of either pulse width problems or triggering difficulties.
The purpose of this note is to present an overall view of
what one-shots are, how they work, and how to use them
properly. It is intended to give the reader comprehensive
information which will serve as a designers guide to oneshots.
DEFINITION
A one-shot integrated circuit is a device that, when triggered, produces an output pulse width that is independent
of the input pulse width, and can be programmed by an
external Resistor-Capacitor network. The output pulse width
will be a function of the RC time constant. There are various
one-shots manufactured by National Semiconductor that
have diverse features, although, all one-shots have the basic property of producing a prorammable output pulse width.
All National one-shots have True and Complementary outputs, and both positive and negative edge-triggered inputs.
National Semiconductor
Application Note 366
Kern Wong
July 1984
Designers Encyclopedia of
One-Shots
Per
IC
Package
Retrigger
Reset
Capacitor
Min
Max
in mF
Resistor
Min
Max
in Kohms
Timing Equation*
for
CEXT n 1000 pF
30
40
tW e KRC # (1 a 0.7/R)
K & 0.7
None
None
5
5
180
260
tW e KRC
K & 0.37
Yes
Yes
None
None
5
5
25
50
tW e KRC # (1 a 0.7/R)
K & 0.34
Yes
Yes
Yes
Yes
None
None
5
5
200
400
tW e KRC # (1 a 0.7/R)
K & 0.29
Two
Two
Yes
Yes
Yes
Yes
None
None
5
5
180
260
tW e KRC
K & 0.37
DM54LS221
DM74L5221
Two
Two
No
No
Yes
Yes
1.4
1.4
70
100
tW e KRC
K & 0.7
DM7853
DM8853
Two
Two
Yes
Yes
Yes
Yes
None
None
5
5
25
50
tW e KRC # (1 a 1/R)
K & 0.31
DM8601
DM9601
One
One
Yes
Yes
No
No
None
None
5
5
25
50
tW e KRC # (1 a 0.7/R)
K & 0.34
DM8602
DM9602
Two
Two
Yes
Yes
Yes
Yes
None
None
5
5
25
50
tW e KRC # (1 a 1/R)
K & 0.34
One
One
No
No
No
No
DM54LS122
DM74L5122
One
One
Yes
Yes
Yes
Yes
DM54123
DM74123
Two
Two
Yes
Yes
DM54L123
DM74L123
Two
Two
DM54LS123
DM74L5123
0
0
1000
1000
0
0
1000
1000
*The above timing equations hold for all combinations of REXT and CEXT for all cases of CEXT l 1000 pF within specified limits on the
REXT and CEXT. K can be treated as an invariant for CEXT n 1000 pF. Refer to K vs CEXT curves.
C1995 National Semiconductor Corporation
TL/F/6738
RRD-B30M105/Printed in U. S. A.
AN-366
1.4
1.4
DM54121
DM74121
DM74121
TL/F/6738 1
DM74123
DM74LS123
DM74LS221
TL/F/6738 2
DM9602
DM74LS123
DM74123
TL/F/6738 4
DM9602
DM74121
The following graphs show the dependence of the pulse width on VCC.
As with any IC applications, the device
should be properly bypassed so that
large transient switching currents can
be easily supplied by the bypass capacitor. Capacitor values of 0.001 mF
to 0.10 mF are generally used for the
VCC bypass capacitor.
TL/F/6738 5
DM74123
DM74LS123
DM74LS221
TL/F/6738 6
DM74121
TL/F/6738 7
DM74123
DM74LS123
DM74LS221
TL/F/6738 8
DM74121
TL/F/6738 9
DM74LS123
DM74LS221
TL/F/6738 10
Truth Tables
Connection Diagrams
121 One-Shots
Inputs
A1
A2
L
X
X
H
H
X
L
X
H
v
v
H
H
L
X
H
H
H
L
X
X
L
u
u
L
L
L
L
H
H
H
H
74121 (N)
Outputs
Outputs
TL/F/6738 11
H
L
Clear
A1
A2
B1
B2
L
X
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
L
L
L
X
X
X
H
X
H
X
X
X
X
X
L
L
L
X
X
L
X
H
X
X
X
L
H
H
v
v
u
u
L
X
L
L
L
L
L
H
H
H
H
H
e
e
e
e
e
e
e
X
u
v
v
v
H
X
L
u
H
H
u
H
H
H
H
H
H
u
H
H
u
H
H
H
H
H
Top View
54LS122 (J, W);
HIGH Level
LOW Level
Transition from LOW-to-HIGH
Transition from HIGH-to-LOW
One HIGH Level Pulse
One LOW Level Pulse
Dont Care
74LS122 (N)
TL/F/6738 12
Top View
123, L123A
Inputs
Outputs
CLR
H
X
L
X
L
H
H
H
H
L
L
L
H
H
H
X
TL/F/6738 13
Top View
54LS123 (J, W);
LS123
Inputs
74LS123 (N)
Outputs
Clear
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
u
H
H
TL/F/6738 14
Top View
9602 (J, W);
8602 (N)
8602
Pin Numbers
H
L
CLR
HxL
H
X
L
LxH
X
H
H
L
e
e
e
e
e
e
e
X
u
v
Operation
Trigger
Trigger
Reset
HIGH Level
LOW Level
Transition from LOW-to-HIGH
Transition from HIGH-to-LOW
One HIGH Level Pulse
One LOW Level Pulse
Dont Care
TL/F/6738 15
Top View
6
Dt
CD
Operation
LxH
H
HxL
L
HxL
LxH
X
L
HxL
H
LxH
Same as t
Same as t
X
H
H
H
H
H
H
L
Trigger
Trigger
Trigger
Trigger
Trigger
Trigger
Reset
8853 (N)
TL/F/6738 16
Top View
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
74LS221 (N)
Outputs
u
H
H
TL/F/6738 17
Top View
8601
Inputs
A2
B1
B2
H
X
X
L
L
L
X
X
X
H
H
X
X
X
X
X
L
L
L
X
L
X
H
X
X
L
H
H
L
L
L
L
H
H
H
H
v
v
H
L
e
e
e
e
e
e
e
X
u
v
Outputs
A1
v
v
H
u
H
H
u
H
H
H
H
u
H
H
u
H
H
H
HIGH Level
LOW Level
Transition from LOW-to-HIGH
Transition from HIGH-to-LOW
One HIGH Level Pulse
One LOW Level Pulse
Dont Care
8601 (N)
TL/F/6738 18
Top View
7
Device
Number
IC
Package
Retrigger
Reset
Capacitor
Min
Max
in mF
Resistor
Min
Max
in Kohms
Timing Equation
for
CEXT l 1000 pF
MM54HC123
MM74HC123
Two
Two
Yes
Yes
Yes
Yes
None
None
2
2
*
*
tW e RC
MM54C221
MM74C221
Two
Two
No
No
Yes
Yes
None
None
5
5
*
*
tW e RC
MM54HC221
MM74HC221
Two
Two
No
No
Yes
Yes
None
None
2
2
*
*
tW e RC
MM54HC423
MM74HC423
Two
Two
Yes
Yes
Yes
Yes
None
None
2
2
*
*
tW e RC
CD4528BM
CD4528BC
Two
Two
Yes
Yes
Yes
Yes
None
None
5
5
*
*
CD4538BM
CD4538BC
Two
Two
Yes
Yes
Yes
Yes
None
None
5
5
*
*
tW e RC
MM54HC4538
MM74HC4538
Two
Two
Yes
Yes
Yes
Yes
None
None
1
1
*
*
tW e KRC
K & 0.74
CD4047BM*
CD4047BC
One
One
Yes
Yes
Yes
Yes
None
None
0.5
0.5
*
*
tW e KRC
K & 1.38
*Maximum usable resistance RX is a function of the leakage of the capacitance CX of the device, and leakage due to board layout, surface resistance, etc.
**This device is a monostable/astable multivibrator.
The arrow indicates the divergent point where timing resistor values beyond which results in outputs remaining indefinitely at a logic HIGH level.
MM74C221
MM74HC123
MM14528
CD4528
MM74HC221
MM14538
CD4538
MM74HC4538
TL/F/6738 19
Outputs
Clear
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
u
H
H
TL/F/6738 20
Top View
Timing Component
MM54HC423/MM74HC423
54HC423 (J); 74HC423 (J, N)
Inputs
Outputs
Clear
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
TL/F/6738 21
MM54HC4538/MM74HC4538
54HC4538 (J); 74HC4538 (J, N)
Inputs
Outputs
Clear
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
e HIGH Level
e LOW Level
u
v
TL/F/6738 22
Top View
e Dont Care
MM54C221
MM74C221
Inputs
H
L
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
e HIGH Level
e
e
e
e
e
e
X
u
v
Outputs
Clear
LOW Level
Transition from LOW-to-HIGH
Transition from HIGH-to-LOW
One HIGH Level Pulse
One LOW Level Pulse
Dont Care
TL/F/6738 23
Top View
Timing Component
TL/F/6738 24
Block Diagrams
RX and CX Are External Timing Components
TL/F/6738 25
10
Typical K Coefficient
Variation vs Supply Voltage
MM54/74 HC4538
TL/F/6738 26
TL/F/6738 27
MM54/74C221
Typical Distribution of Units for
Output Pulse Width
TL/F/6738 29
TL/F/6738 28
11
MM54/74C221 (Continued)
Typical Performance Characteristics
Typical Distribution of Units for
Output Pulse Width
TL/F/6738 31
TL/F/6738 30
CD4047BM/CD4047BC
Block and Connection Diagrams
TL/F/6738 32
TL/F/6738 33
Top View
12
CD4047 (Continued)
Truth Table
Terminal Connections
Function
To VDD
To VSS
Input Pulse To
Astable Multivibrator
Free-Running
True Gating
Complement Gating
4, 5, 6, 14
4, 6, 14
6, 14
7, 8, 9, 12
7, 8, 9, 12
5, 7, 8, 9, 12
5
4
10, 11, 13
10, 11, 13
10, 11, 13
Monostable Multivibrator
Positive Edge-Trigger
Negative Edge-Trigger
Retriggerable
4, 14
4, 8, 14
4, 14
5, 6, 7, 9, 12
5, 7, 9, 12
5, 6, 7, 9
8
6
8, 12
10, 11
10, 11
10, 11
14
5, 6, 7, 8, 9, 12
External Countdown*
(See Figure *)
(See Figure *)
(See Figure *)
Note: External resistor between terminals 2 and 3; external capacitor between terminals 1 and 3.
TL/F/6738 34
Timing Diagrams
Astable Mode
Monostable Mode
TL/F/6738 35
TL/F/6738 36
Retrigger Mode
TL/F/6738 37
13
CD4047 (Continued)
Typical Performance Characteristics
Typical Q, Q, Pulse Width
Accuracy vs Supply Voltage
(Monostable Mode Operation)
TL/F/6738 39
TL/F/673838
A
B
C
D
E
fQ, Q
1000 kHz
100 kHz
10 kHz
1 kHz
100 Hz
R
22k
22k
220k
220k
2.2M
C
10 pF
100 pF
100 pF
1000 pF
1000 pF
A
B
C
D
E
tM
2 ms
7 ms
60 ms
550 ms
5.5 ms
R
22k
22k
220k
220k
2.2M
C
10 pF
100 pF
100 pF
1000 pF
1000 pF
TL/F/6738 41
TL/F/673840
A
B
C
D
fQ, Q
1000 kHz
100 kHz
10 kHz
1 kHz
R
22k
22k
220k
220k
C
10 pF
100 pF
100 pF
1000 pF
A
B
C
D
14
tM
2 ms
7 ms
60 ms
500 ms
R
22k
22k
220k
220k
C
10 pF
100 pF
100 pF
1000 pF
CD4528BM/CD4528BC
Block and Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/6738 42
Top View
Truth Table
Inputs
H
L
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
e
e
e
e
e
e
e
X
u
v
Outputs
Clear
TL/F/6738 43
Top View
HIGH Level
LOW Level
Transition from LOW-to-HIGH
Transition from HIGH-to-LOW
One HIGH Level Pulse
One LOW Level Pulse
Dont Care
Pulse Width vs CX
TL/F/6738 44
TL/F/6738 45
15
H
L
L
X
X
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
e
e
e
e
e
e
e
X
u
v
Outputs
Clear
HIGH Level
LOW Level
Transition from LOW-to-HIGH
Transition from HIGH-to-LOW
One HIGH Level Pulse
One LOW Level Pulse
Dont Care
TL/F/6738 46
CD4538BM, CD4538BC
Typical Performance Characteristics
Typical Normalized
Distribution of Units for
Output Pulse Width
TL/F/6738 47
16
CD4538 (Continued)
Typical Performance Characteristics
Typical Total Supply
Current vs Output Duty
Cycle, RX e 100 kX,
CL e 50 pF, CX e 100 pF
(One Monostable
Switching Only)
TL/F/6738 48
TL/F/6738 49
Truth Table
Inputs
Output
EPos
ENeg
L
H
H
H
L
H
TL/F/6738 50
H e HIGH Level
L e LOW Level
17
(Continued)
MC10198
Pulse Width vs
Temperature and
Supply Voltage
Pulse Width vs
IT @ CEXT e 13 pF
TL/F/6738 52
TL/F/673851
MC10198
Timing Pulse Width vs
CEXT and REXT
Recovery Time vs
CEXT @ IT e 5 mA
TL/F/673853
TL/F/6738 54
Note: The MC10198 is made by Motorola and the DM74HC4538 is also a Motorola-designed part, which is a cooperative trade part of the HC one-shots between
NSC and Motorola. Information courtesy of Motorola Inc.
OPERATING RULES
In all cases, R and C represented by the timing equations
are the external resistor and capacitor, called REXT and
CEXT, respectively, in the data book. All the foregoing timing
equations use C in pF, R in Kohms, and yield tW in nanoseconds. For those one-shots that are not retriggerable, there
is a duty cycle specification associated with them that defines the maximum trigger frequency as a function of the
external resistor, REXT.
In all cases, an external (or internal) timing resistor (REXT)
connects from VCC or another voltage source to the REXT/
CEXT pin, and an external timing capacitor (CEXT) connects between the REXT/CEXT and CEXT pins are required for proper operation. There are no other elements
needed to program the output pulse width, though the value
of the timing capacitor may vary from 0.0 to any necessary
value.
When connecting the REXT and CEXT timing elements, care
must be taken to put these components absolutely as close
to the device pins as possible, electrically and physically.
Any distance between the timing components and the device will cause time-out errors in the resulting pulse width,
because the series impedance (both resistive and inductive)
18
high-grade mica glass, polystyrene, polypropylene, or polycarbonate capacitor may be used. For large time constants,
use a solid tantalum or special aluminum capacitor.
In general, if small timing capacitor has leakage approaching 100 nA or if the stray capacitance from either terminal to
ground is greater than 50 pF, then the timing equations or
design curves which predict the pulse width would not represent the programmed pulse width which the device generates.
When an electrolytic capacitor is used for CEXT, a switching
diode is often suggested for standard TTL one-shots to prevent high inverse leakage current (Figure 1) . In general, this
switching diode is not required for LS-TTL, CMOS, and
HCMOS devices; it is also not recommended with retriggerable applications.
TL/F/6738 57
FIGURE 3
tRET e tW a tPLH e K # (REXT)(CEXT) a tPHL
TL/F/6738 55
FIGURE 1
It is never a good practice to Ieave any unused inputs of a
logic integrated circuit floating. This is particularly true for
one-shots. Floating uncommitted inputs or attempts to establish a logic HIGH level in this manner will result in malfunction of some devices.
Operating one-shots with values of the REXT outside the
recommended limits is at the risk of the user. For some
devices it will lead to complete inoperation, while for other
devices it may result in either pulse widths different from
those values predicted by design charts or equations, or
with modes of operation and performance quite different
from known standard characterizations.
To obtain variable pulse width by remote trimming, the following circuit is recommended (Figure 2) . Remote should
be placed as close to the one-shot as possible.
TL/F/6738 56
FIGURE 2
VCC and ground wiring should conform to good high frequency standards and practices so that switching transients
on the VCC and ground return leads do not cause interaction between one-shots. A 0.001 mF to 0.1 mF bypass capacitor (disk or monolithic type) from the VCC pin to ground
is necessary on each device. Furthermore, the bypass capacitor should be located so as to provide as short an electrical path as possible between the VCC and ground pins. In
severe cases of supply-line noise, decoupling in the form of
a local power supply voltage regulator is necessary.
For retriggerable devices the retrigger pulse width is calculated as follows for positive-edge triggering:
TL/F/6738 58
FIGURE 4
The LS221 trigger on CLEAR: This mode of trigger requires first the B-Input be set from a Low-to-High level
while the CLEAR input is maintained at logic Low level.
Then, with the B Input at logic High level, the CLEAR
19
input, whose positive transition from LOW-to-HIGH will trigger an output pulse (A input is LOW).
FIGURE 5
TL/F/673860
TL/F/6738 61
DM54LS123 One-Shot
TL/F/6738 62
20
TL/F/6738 64
TL/F/6738 63
Note: Textool 16 Pin DUT socket, do not use sockets for K1, 2.
FIGURE 7b
Applications
The following circuits are shown with generalized one-shot
connection diagram.
Noise Discriminator (Figure 8)
The time constant of the one-shot (O-S) can be adjusted so
that an Input pulse width narrower than that determined by
the time constant will be rejected by the circuit. Output at Q2
wiIl follow the desired input pulse, with the leading edge de-
TL/F/6738 65
21
TL/F/6738 66
output pulse train is integrated by R1 and C1 to yield a waveform whose amplitude is proportional to the input frequency.
(Retriggerable device required.)
TL/F/6738 68
TL/F/673867
TL/F/6738 70
TL/F/673869
TL/F/6738 71
22
TL/F/6738 72
DUTY CYCLE e
FREQ e
RX2 CX2
RX1 CX1
1
K RX1 CX1
TL/F/6738 73
TL/F/6738 74
TL/F/6738 75
FIGURE 12. Delayed Pulse Generator with Override To Terminate Output Pulse
23
is missing in the incoming pulse train, which then triggers OS2 and produces an indicating pulse at Q2. (Retriggerable
device required.)
TL/F/6738 76
TL/F/6738 77
TL/F/6738 78
24
TL/F/6738 79
The band pass of the circuit is determined by the time constants of the two low-pass filters represented by O-S1 and
O-S2. With the output at Q2 delayed by C, the D-FF clocks
HIGH only when the cutoff frequency of O-S2 has been ex-
TL/F/6738 80
TL/F/6738 81
TL/F/6738 82
26
The next clock pulse (the second bit cell) is ANDed with
a CLK WINDOW and becomes the next b SEP CLK, which
will reset the R-S FF and trigger O-S1. As O-S1 becomes
active, the a DATA WINDOW becomes active, enabling the
first AND gate. With no data bit in the second bit cell, the
R-S FF will remain reset, enabling the D-FF to be clocked
off when a DATA WINDOW falls. When the D-FF is clocked
off, Q4 will hold O-S1 reset and allow O-S2 to be triggered.
The third clock pulse (bit cell 3) is ANDed with a CLK
WINDOW and becomes bSEP CLK, which continues re-
TL/F/6738 83
27
ing circuit be connected to the output of the op-amp to prevent the VCO control voltage from going negative or more
positive than necessary. A back-to-back diode pair connected between the op-amp and the VCO is highly recommended, for it will present a high impedance to the VCO input
during locked mode. This way, stable and smooth operation
of the PLO circuit is assured.
TL/F/6738 84
TL/F/6738 85
28
A FlNAL NOTE
ACKNOWLEDGEMENT
It is hoped that this brief note will clarify many pertinent and
subtle points on the use and testing of one-shots. We invite
your comments to this application note and solicit your constructive criticism to help us improve our service to you.
29
AN-366
National Semiconductor
Europe
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Email: cnjwge @ tevm2.nsc.com
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Fax: (852) 2736-9960
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Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.