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TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
3 Description
The TPS62410 device is a synchronous dual stepdown DCDC converter. It provides two independent
output voltage rails powered by 1-cell Li-Ion or 3-cell
NiMH/NiCD batteries. The device is also suitable to
operate from a standard 3.3 V or 5 V voltage rail.
2 Applications
PACKAGE
TPS62410
VSON (10)
3.00 mm 3.00 mm
TPS62410
VIN
100
FB 1
SW1
CIN
L1
2.2 H
10 F
R11
270k
DEF_1
L2
EN_2
MODE/
DATA
SW2
2.2 H
80
COUT1 = 22 F
70
V OUT2 = 1.8V
Cff2
R21
360k 33pF
ADJ2
GND
R22
180k
Up to 800mA
COUT2 = 22 F
VOUT = 3.3 V
VIN = 3.6 V
up to 800mA
R12
180k
EN_1
90
VOUT1 = 1.5V
Efficiency - %
VIN 2.5V 6V
VIN = 3.6 V
60
VIN = 5 V
VIN = 5 V
50
40
30
20
10
0
0.01
0.1
10
IOUT - mA
100
1000
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2007) to Revision A
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
TPS62410
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ADJ2
10
SW2
MODE/DATA
EN2
VIN
GND
FB1
EN1
DEF_1
SW1
Thermal Pad
Pin Functions
PIN
NAME
NO.
ADJ2
I/O
DESCRIPTION
Input to adjust output voltage of converter 2. In adjustable version (TPS62410) connect an external
resistor divider between VOUT2, this pin and GND to set output voltage between 0.6 V and VIN. If
EasyScale interface is used for converter 2, this pin must be directly connected to the output.
MODE/DATA
VIN
FB1
Direct feedback voltage sense input of converter 1, connect directly to VOUT1. An internal feed forward
capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions
or when the Interface is used, this pin is connected to an internal resistor divider network.
DEF_1
I/O
This pin defines the output voltage of converter 1. The pin acts in TPS62410 as an analog input for
output voltage setting through external resistors. In fixed default output voltage versions this pin is a
digital input to select between two fixed default output voltages.
In TPS62410 an external resistor network needs to be connected to this pin to adjust the default output
voltage.
SW1
EN1
GND
GND for both converters, this pin should be connected with the PowerPAD
EN2
I/O
SW2
10
PowerPAD
Connect to GND
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Input voltage on VIN
(2)
MIN
MAX
UNIT
0.3
0.3
VIN +0.3, 7
500
A
V
0.3
0.3
VIN +0.3, 7
150
40
85
Tstg
Storage temperature
65
150
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Electrostatic discharge
2000
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Supply voltage
MIN
MAX
2.5
UNIT
V
0.6
VIN
TA
-40
85
TJ
-40
125
(1)
DRC (VSON)
UNIT
10 PINS
RJA
45.9
C/W
RJC(top)
64.3
C/W
RJB
20.4
C/W
JT
1.3
C/W
JB
20.6
C/W
RJC(bot)
2.8
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
TPS62410
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
19
29
32
48
23
3.6
mA
1.2
0.1
Falling
1.5
2.35
SUPPLY CURRENT
VIN
Input voltage
IQ
ISD
Shutdown current
VUVLO
2.5
Rising
2.4
1.2
VIN
VIL
0.4
IIN
0.05
0.01
DEF_1 INPUT
IIN
MODE/DATA
VIH
1.2
VIN
VIL
0.4
IIN
VOH
VOL
0.01
0
VIN
0.4
INTERFACE TIMING
tStart
Start time
tH_LB
tL_LB
tL_HB
2
2
200
2 x tH_LB
400
200
tH_LB
2 x tL_HS
400
TEOS
End of Stream
TEOS
tACKN
Duration of acknowledge
condition (MODE/DATE line
pulled low by the device)
VIN 2.5 V to 6 V
(1)
(2)
(3)
2
400
520
Device is switching with no load on the output, L = 3.3 H, value includes losses of the coil
These values are valid after the device has been already enabled one time (EN1 or EN2 = High) and supply voltage VIN has not
powered down.
After the first enable, these values are valid when the device is disabled (EN1 and EN2 = Low) and supply voltage VIN is powered up.
The values remain valid until the device has been enabled first time (EN1 or EN2 = High).
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TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
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TEST CONDITIONS
MIN
tvalACK
ttimeout
Time-out for entering power-save MODE/DATA Pin changes from high to low
mode
TYP
MAX
UNIT
520
280
620
200
450
7.5
1.2
1.38
POWER SWITCH
RDS(ON)
ILK_PMOS
VDS = 6.0 V
RDS(ON)
ILK_SW1/SW
ILIMF
Forward current
limit PMOS and
NMOS
TSD
Thermal shutdown
150
20
OSCILLATOR
fSW
Oscillator frequency
2.25
2.5
MHz
OUTPUT
VOUT
Vref
Reference voltage
0.6
Voltage positioning active, MODE/DATA =
GND, device operating in PFM mode, VIN =
2.5 V to 5.0 V (6) (7)
VOUT (PFM)
VOUT
VIN
600
1.5%
1.01 x VOUT
2.5%
1%
0%
1%
1%
0%
1%
V
mV
0.5
%/A
tStart up
Start-up time
170
tRamp
750
(4)
(5)
(6)
(7)
(8)
(9)
PACKAGE
DRC
2050 mW
21 mW/C
TPS62410
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2.5
2.45
23
2.4
85C
22
Iddq - mA
Fosc - MHz
2.35
2.3
-40C
2.25
2.2
20
25C
2.15
25C
21
-40C
19
85C
2.1
18
2.05
2
2.5
3.5
4.5
VIN - V
17
2.5
5.5
3.5
4.5
5.5
VIN - V
42
0.5
40
0.45
38
RDSon - W
Iddq - mA
85C
36
25C
34
0.4
85C
0.35
25C
0.3
32
-40C
0.25
-40C
30
0.2
0.15
2.5
28
2.5
3.5
4.5
5.5
3.5
VIN - V
4.5
5.5
VIN - V
0.3
0.25
RDSon - W
85C
0.2
25C
-40C
0.15
0.1
0.05
2.5
3.5
4.5
5.5
VIN - V
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
7 Detailed Description
7.1 Overview
7.1.1 Operation
The TPS62410 includes two synchronous step-down converters. The converters operate with typically 2.25-MHz
fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If power-save mode is
enabled, the converters automatically enter power-save mode at light load currents and operate in pulse
frequency modulation (PFM). During PWM operation the converters use a unique fast response voltage mode
controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of
small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the
P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the
control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the NMOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC/DC converters operate synchronized to each other. A 180 phase shift between converter 1 and
converter 2 decreases the input RMS current.
7.1.1.1 Converter 1
In the adjustable output voltage version TPS62410 the converter 1 output voltage can be set through an external
resistor network on pin DEF_1, which operates as an analog input. In this case, the output voltage can be set in
the range of 0.6 V to VIN. The FB1 pin must be directly connected to the converter 1 output voltage VOUT1. It
feeds back the output voltage directly to the regulation loop.
The output voltage of converter 1 can also be changed by the EasyScale serial interface. This makes the
device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network.
7.1.1.2 Converter 2
In the adjustable output voltage version TPS62410, the converter 2 output voltage is set by an external resistor
divider connected to ADJ2 pin and uses an external feed forward capacitor of 33 pF.
It is also possible to change the output voltage of converter 2 through the EasyScale interface. In this case, the
ADJ2 pin must be directly connected to converter 2 output voltage VOUT2. At TPS62410 no external resistor
network may be connected.
TPS62410
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PMOS Current
Limit Comparator
Converter 1
VIN
FB_VOUT
Thermal
Shutdown
Softstart
VREF +1%
Skip Comp.
EN1
FB_VOUT
VREF- 1%
DEF1
VREF
Control
Stage
Error Amp.
Internal
FB
VOUT1 compensated
Int. Resistor
Network
PWM
Comp.
Cff 25pF
SW1
MODE
Register
RI 1
RI..N
Sawtooth
Generator
DEF1_High
RI3
FB1
Gate Driver
GND
DEF1_Low
Average
Current Detector
Skip Mode Entry
Note A
NMOS Current
Limit Comparator
CLK 0
Reference
Mode/
DATA
Easy Scale
Interface
ACK
MOSFET
Open drain
Load Comparator
2.25MHz
Oscillator
Undervoltage
Lockout
PMOS Current
Limit Comparator
CLK 180
VIN
FB_VOUT
Converter 2
Int. Resistor
Network
VREF +1%
Skip Comp.
Register
FB_VOUT
DEF2
Note B
Cff 25pF
VREF- 1%
VREF
Error Amp.
RI 1
Internal
compensated
RI..N
Control
Stage
Gate Driver
PWM
Comp.
SW2
MODE
FB_VOUT2
ADJ2
Thermal
Shutdown
Softstart
Sawtooth
Generator
CLK 180
GND
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
EN2
Load Comparator
GND
A.
In fixed output voltage version, the pin DEF_1 is connected to an internal digital input and disconnected from the error
amplifier
B.
To set the output voltage of converter 2 through EasyScale interface, ADJ2 pin must be directly connected to VOUT2
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
+1%
PFM Mode
light load
VOUT_NOM
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
COMP_LOW threshold 1%
10
TPS62410
www.ti.com
EN
95%
5%
VOUT
tStartup
tRAMP
Figure 7. Soft-Start
7.4.2 100% Duty Cycle Low Dropout Operation
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range; that is, the minimum input voltage to maintain regulation depends on the load current and output
voltage, and can be calculated as:
Vin min + Vout max ) Iout max
RDSonmax ) R L
where
(1)
With decreasing load current, the device automatically switches into pulse-skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current maintaining high efficiency.
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11
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
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(2)
(3)
In order to keep the output voltage ripple in power-save mode low, the output voltage is monitored with a single
threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip
comp) of 1.01 VOUTnominal, the corresponding converter starts switching for a minimum time period of typically 1
s and provides current to the load and the output capacitor. Therefore the output voltage increases and the
device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this
moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied
by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device
starts switching again. The power-save mode is exited and PWM mode entered in case the output current
exceeds the current IOUT_PFM_leave, or if the output voltage falls below a second comparator threshold, called
skip comparator low (skip comp Low) threshold. This skip comparator low threshold is set to 2% below nominal
Vout, and enables a fast transition from power-save mode to PWM mode during a load step. In power-save mode
the quiescent current is reduced typically to 19 A for one converter and 32 A for both converters active. This
single skip comparator threshold method in power-save mode results in a very low output voltage ripple. The
ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values
minimizes the output ripple. The power-save mode can be disabled through the MODE/DATA pin set to high.
Both converters then operate in fixed PWM mode. Power-save mode enable/disable applies to both converters.
7.4.4 Short Circuit Protection
Both outputs are short circuit protected with maximum output current = ILIMF (P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it will be turned off and the NMOS turned on. The PMOS only turns on
again, once the current in the NMOS decreases below the NMOS current limit.
12
TPS62410
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7.5 Programming
7.5.1 EasyScale Interface: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
7.5.1.1 General
The EasyScale interface is a simple but very flexible one-pin interface to configure the output voltage of both
DCDC converters. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 8 and Table 1 give an overview of the protocol. The protocol consists
of a device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data
byte consists of five bit for information, two address bits and the RFA bit. RFA bit set to high indicates the
Request For Acknowledge condition. The acknowledge condition is only applied if the protocol was received
correctly.
The advantage of EasyScale interfaces compared to other one-pin interfaces is that its bit detection is, to a
large extent, independent from the bit transmission rate. It can automatically detect bit rates between 1.7 kbps
and up to 160 kbps. Furthermore, the interface is shared with the MODE/DATA pin and requires therefore no
additional pin.
7.5.1.2 Protocol
All bits are transmitted MSB first and LSB last. Figure 9 shows the protocol without acknowledge request (bit
RFA = 0), Figure 10 with acknowledge (bit RFA = 1) request.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the
MODE/DATA pin needs to be pulled high for at least tStart before the bit transmission starts with the falling edge.
In case the MODE/DATA line was already at high level (forced PWM mode selection) no start condition need be
applied prior the device address byte.
The transmission of each byte needs to be closed with an end-of-stream condition for at least TEOS.
7.5.1.3 Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can
be simplified to:
High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 11
Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 11
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge.
Depending on the relation between tLow and tHigh a 0 or 1 is detected.
7.5.1.4 Acknowledge
The acknowledge condition is only applied if:
acknowledge is requested by a set RFA bit
the transmitted device address matches with the device address of the device
16 bits were received correctly
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is max. 520 s. The acknowledge condition is valid after an internal delay time tvalACK. This means
the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected.
The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after
tvalACK and read back a 0.
In case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied,
thus the internal MOSFET will not be turned on and the external pullup resistor pulls MODE/DATA pin high after
tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends.
13
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
Programming (continued)
NOTE
The acknowledge condition may only be requested in case the master device has an
open-drain output.
In case of a push-pull output stage, TI recommends to use a series resistor in the MODE/DATA line to limit the
current to 500 A in case of an accidentally requested acknowledge to protect the internal ACKN-MOSFET.
7.5.1.5 MODE Selection
Because of the MODE/DATA pin is used for two functions, interface and a mode selection, the device needs to
determine when it has to decode the bit stream or to change the operation mode.
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.
The device stays also in forced PWM mode during the whole time of a protocol reception.
With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at
least ttimeout, the device gets an internal time-out and power-save mode operation is enabled.
A protocol which is sent within this time will be ignored, because the falling edge for the mode change will be first
interpreted as start of the first bit. In this case, TI recommends to send first the protocol and change at the end of
the protocol to power-save mode.
DATA IN
Start
Start
Device Address
DA7 DA6 DA5 DA4
0
1
0
0
DATABYTE
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT
ACK
Device
Address
Byte
4Ehex
Data
Byte
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
DESCRIPTION
DA7
IN
DA6
IN
DA5
IN
DA4
IN
DA3
IN
DA2
IN
DA1
IN
IN
DA0
7 (MSB)
RFA
A1
Address bit 1
A0
Address bit 0
D4
D3
D2
Data bit 2
D1
Data bit 1
0 (LSB)
D0
Data bit 0
ACK
Request for acknowledge, if High, acknowledge condition will applied by the device
IN
OUT
Data bit 4
Data bit 3
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open-drain output, Line needs to be pulled high by the host with a pullup
resistor.
This feature can only be used if the master has an open-drain output stage. In case
of a push-pull output stage acknowledge condition may not be requested.
14
TPS62410
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tStart
DATA IN
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
RFA
0
TEOS
D0
1
TEOS
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
D0
1
RFA
1
T EOS
tvalACK
ACKN
tACKN
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pull
down
tLow
tHigh
Low Bit
(Logic 0)
tLOW
tHigh
High Bit
(Logic 1)
ttimeout
Power Save Mode
15
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
tStart
DATA Byte
MODE/DATA
TEOS
TEOS
ttimeout
A0
REG_DEF_1_High
REGISTER
REG_DEF_1_Low
REG_DEF_2
Do not use
16
DESCRIPTION
D4
D3
D2
D1
D0
TPS62410
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D4
D3
D2
D1
D0
0.825
0.85
0.875
0.9
0.925
0.95
0.975
1.0
1.025
10
1.050
11
1.075
12
1.1
13
1.125
14
1.150
15
1.175
16
1.2
17
1.225
18
1.25
19
1.275
20
1.3
21
1.325
22
1.350
23
1.375
24
1.4
25
1.425
26
1.450
27
1.475
28
1.5
29
1.525
30
1.55
31
1.575
17
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
D4
D3
D2
D1
D0
18
0.85
0.9
0.95
1.0
1.05
1.1
1.15
1.2
1.25
10
1.3
11
1.35
12
1.4
13
1.45
14
1.5
15
1.55
16
1.6
17
1.7
18
1.8
19
1.85
20
2.0
21
2.1
22
2.2
23
2.3
24
2.4
25
2.5
26
2.6
27
2.7
28
2.8
29
2.85
30
3.0
31
3.3
TPS62410
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R
1 ) 11
R 12
To keep the operating current to a minimum, TI recommends selecting R12 within a range of 180 k to 360 k.
The sum of R12 and R11 should not exceed approimately1 M. For higher output voltages than 3.3 V, TI
recommends choosing lower values than 180 k for R12. Route the DEF_1 line away from noise sources, such
as the inductor or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. An internal
feed-forward capacitor is connected to this pin, therefore there is no need for an external feed-forward capacitor
for converter 1.
8.1.1.2 Converter 2
The default output voltage of converter 2 can be set by an external resistor network. For converter 2 the same
recommendations apply as for converter 1. In addition to that, a 33-pF external feed-forward capacitor Cff2 for
good load transient response must be used.
The output voltage can be calculated to:
V OUT + VREF
R
1 ) 21
R 22
Route the ADJ2 line away from noise sources, such as the inductor or the SW2 line. In case the interface is used
for converter 2, connect ADJ2 pin directly to VOUT2
19
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
FB 1
VIN
L1
SW1
CIN
10 mF
2.2 mH
DEF_1
COUT1 = 22 mF
R12
180 kW
EN_1
EN_2
R11
270 kW
VOUT1 = 1.5 V
up to 800 mA
L2
SW2
3.3 mH
MODE/
DATA
ADJ2
GND
R21
Cff2
825 kW 33 pF
VOUT2 = 2.85 V
up to 800 mA
COUT2 = 22 mF
R22
220 kW
Figure 14. Typical Application Circuit 1.5-V and 2.85-V Adjustable Outputs, Low PFM Voltage Ripple
Optimized
8.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs by choosing
appropriate external components. The following design procedure is adequate for whole VIN, VOUT and load
current range of TPS62410.
8.2.2 Detailed Design Procedure
8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
The device is optimized to operate with inductors of 2.2 H to 4.7 H and output capacitors of 10 F to 22 F.
For operation with a 2.2 H inductor, a 22 F capacitor is suggested.
8.2.2.1.1 Inductor Selection
The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the
inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance
should be selected for highest efficiency.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is
recommended because during heavy load transient the inductor current will rise above the calculated value.
DI L + Vout
1 * Vout
Vin
I Lmax + I outmax )
(6)
DI L
2
where
20
(7)
TPS62410
www.ti.com
INDUCTOR TYPE
SUPPLIER
VLF3014
TDK
3 3 1.4
LPS3015
Coilcraft
LPS4018
Coilcraft
The advanced fast response voltage mode control scheme of the two converters allows the use of small ceramic
capacitors with a typical value of 10 F, without having large output voltage undershoots and overshoots during
heavy load transients. Ceramic X7R/X5R capacitors having low ESR values result in lowest output voltage ripple
and are therefore recommended.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. The RMS ripple current is calculated as:
1 * Vout
Vin
I RMSCout + Vout
(8)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
DVout + Vout
1 * Vout
Vin
1
Cout
) ESR
(9)
Where the highest output voltage ripple occurs at the highest input voltage VIN.
At light load currents the converters operate in power-save mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. Higher output capacitors like 22 F values minimize the voltage ripple in PFM mode and tighten DC
output accuracy in PFM mode.
8.2.2.1.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10 F. The input capacitor can be increased
without any limit for better input voltage filtering.
21
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
100
VOUT = 1.2 V
90
80
80
70
70
MODE/DATA = Low
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
60
50
40
30
Efficiency - %
Efficiency - %
VOUT = 1.5 V
MODE/DATA = High
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
50
40
30
20
20
10
10
0
0.01
0.1
10
IOUT - mA
100
MODE/DATA = Low
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
60
0
0.01
1000
10
IOUT - mA
100
1000
100
90
0.1
MODE/DATA = High
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
100
VOUT = 1.8 V
90
VOUT = 3.3 V
80
70
70
VIN = 2.7 V
60
VIN = 2.7 V
VIN = 3.6 V
50
VIN = 3.6 V
VIN = 5 V
40
Efficiency - %
Efficiency - %
VIN = 3.6 V
80
VIN = 5 V
30
20
60
40
10
0.1
10
IOUT - mA
100
0
0.01
1000
0.1
100
MODE/DATA = 0
VOUT = 1.575 V
10
IOUT - mA
100
IOUT = 100 mA
MODE/DATA = 0
VOUT = 3.3 V
IOUT = 10 mA
IOUT = 200 mA
90
1000
100
95
VIN = 5 V
20
90
IOUT = 10 mA
85
80
Efficiency
Efficiency
VIN = 5 V
50
30
10
0
0.01
VIN = 3.6 V
IOUT = 1 mA
75
70
IOUT = 1 mA
80
70
65
60
60
55
50
50
2
22
VIN - V
VIN - V
TPS62410
www.ti.com
1.575
VOUT = 1.5 V
VOUT = 3.3 V
MODE/DATA = low, PFM Mode, Voltage Positioning Active
1.550
VIN = 5 V
VOUT DC - V
VIN = 3.3 V
VIN = 2.7 V
1.500
1.475
VIN = 2.7 V
VIN = 3.3 V
VIN = 3.7 V
VIN = 5 V
VIN = 3.7 V
VOUT DC - V
VIN = 5 V
1.525
PWM Mode
Operation
3.350
VIN = 3.7 V
3.300
VIN = 3.7 V
VIN = 4.2 V
VIN = 4.2 V
VIN = 5 V
3.250
1.450
MODE/DATA = high, forced PWM Mode
1.425
0.01
0.1
10
IOUT - mA
100
1000
IOUT = 10mA
3.200
0.01
0.1
10
IOUT - mA
100
1000
VOUT = 1.8V
IOUT = 400mA
Forced PWM
Mode
MODE/DATA 1V/Div
Enable Power Save Mode
VOUT 20mV/Div
Inductor current 200mA/Div
VOUT = 1.8V
IOUT = 20mA
23
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
VOUT = 1.575V
50mV/Div
www.ti.com
MODE/DATA = low
MODE/DATA = high
PWM Mode operation
VOUT = 1.575V
50mV/Div
IOUT1 = 540mA
IOUT 200mA/Div
IOUT 200mA/Div
IOUT= 60mA
IOUT= 60mA
MODE/DATA = high
VOUT1
500mV/Div
VOUT 1.575
IOUT 200mA
SW1 1V/Div
VOUT 50mV/Div
Icoil 500mA/Div
SW1 5V/Div
SW1 5V/Div
I coil1 200mA/Div
I coil1 200mA/Div
SW2 5V/Div
SW2 5V/Div
Icoil2 200mA/Div
Icoil2 200mA/Div
VIN 3.6V,
VOUT1 : 1.8V
VOUT2 : 3.0V
I OUT1 = I OUT2 = 200mA
VIN 3.6V,
VOUT1: 1.575V
VOUT2: 1.8V
I OUT1 = IOUT2 = 200mA
24
TPS62410
www.ti.com
SW1 5V/Div
I coil1 200mA/Div
SW2 5V/Div
I coil2 200mA/Div
VIN 3.6V,
VOUT1 : 1.2V
VOUT2 : 1.2V
I OUT1 = I OUT2 = 200mA
Figure 33. Typical Operation VIN = 3.6 V, VOUT1 = 1.2 V, VOUT2 = 1.2 V
25
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Take care in the board layout to get the specified performance. If the
layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as
EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short
traces for the main current paths as indicated in bold in Figure 34.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor.
Connect the GND pin of the device to the PowerPAD of the PCB and use this pad as a star point. For each
converter use a common power GND node and a different node for the signal GND to minimize the effects of
ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the
common path to the GND pin, which returns the small signal components and the high current of the output
capacitors as short as possible to avoid ground noise. The output voltage sense lines (FB1, ADJ2, DEF_1)
should be connected right to the output capacitor and routed away from noisy components and traces (that is,
SW line). If the EasyScale interface is operated with high transmission rates, the MODE/DATA trace must be
routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the
MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
CIN
10 F
EN2
MODE/DATA
FB1
L2
SW2
C(OUT2
Cff2
33 pF R21
3.3 H
L1
3.3 H
R11
ADJ2
R22
SW1
COUT2
DEF_1
R12
Thermal Pad
GND
26
TPS62410
www.ti.com
COUT1
CIN
GND Pin
connected
with thermal
pad
COUT2
27
TPS62410
SLVS737A FEBRUARY 2007 REVISED JULY 2015
www.ti.com
11.3 Trademarks
EasyScale, OMAP, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
www.ti.com
4-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TPS62410DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
TPS62410DRCRG4
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
TPS62410DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
TPS62410DRCTG4
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
www.ti.com
4-Aug-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62410 :
Automotive: TPS62410-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
4-Mar-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS62410DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62410DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62410DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62410DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
4-Mar-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62410DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62410DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62410DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS62410DRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
www.ti.com
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