Title Specification Application Author Document Number Date Revision
Title Specification Application Author Document Number Date Revision
Title Specification Application Author Document Number Date Revision
Specification
Application
Author
Document
Number
RDR-158
Date
Revision
1.1
Power Integrations
5245 Hellyer Avenue, San Jose, CA 95138 USA.
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25-Nov-08
Table of Contents
1
2
3
4
Introduction.................................................................................................................4
Power Supply Specification ........................................................................................6
Schematic...................................................................................................................7
Circuit Description ......................................................................................................8
4.1
Input Filter ...........................................................................................................8
4.2
LNK616PG Primary.............................................................................................8
4.3
Output Rectification and Filtering ........................................................................8
4.4
Output Regulation ...............................................................................................9
5 PCB Layout ..............................................................................................................10
6 Bill of Materials .........................................................................................................11
7 Transformer Specification.........................................................................................12
7.1
Electrical Diagram .............................................................................................12
7.2
Electrical Specifications.....................................................................................12
7.3
Materials............................................................................................................13
7.4
Transformer Build Diagram ...............................................................................13
7.5
Transformer Construction..................................................................................14
8 Design Spreadsheet .................................................................................................15
9 Performance Data ....................................................................................................18
9.1
Efficiency ...........................................................................................................18
9.2
Active Mode CEC Measurement Data...............................................................19
9.2.1
Energy Star v1.1 / CEC (2008)...................................................................19
9.2.2
Energy Star v2 (April 2008) ........................................................................20
9.3
No-Load Input Power ........................................................................................21
9.4
Regulation .........................................................................................................22
9.4.1
Load, Line and Temperature ......................................................................22
10
Thermal Performance ...........................................................................................26
10.1 Operating Temperature Survey .........................................................................26
11
Waveforms............................................................................................................27
11.1 Drain Voltage and Current, Normal Operation...................................................27
11.2 Output Voltage Start-up Profile..........................................................................27
11.2.1 No-Load Output Voltage Start-up Characteristic ........................................27
11.2.2 Output Voltage Start-up Characteristic - Resistive Load (5 ) ...................28
11.2.3 Output Voltage Start-up Characteristic - Battery-simulator Load................29
11.3 Drain Voltage and Current Start-up Profile ........................................................30
11.4 Load Transient Response (50% to 100% Load Step) .......................................31
11.5 Output Ripple Measurements............................................................................32
11.5.1 Ripple Measurement Technique ................................................................32
11.5.2 Ripple Measurement Results .....................................................................33
12
Line Surge.............................................................................................................35
13
Conducted EMI .....................................................................................................36
14
Revision History ....................................................................................................38
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Important Note:
Although this board is designed to satisfy safety isolation requirements, the engineering
prototype has not been agency approved. Therefore, all testing should be performed
using an isolation transformer to provide the AC input to the prototype board.
Page 3 of 40
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1 Introduction
This engineering report describes a 5 W constant voltage/constant current (CV/CC)
universal-input power supply for cell phone or similar charger applications. This reference
design is based on the LinkSwitch-II family product LNK616PG.
The LNK616PG was developed to cost effectively replace all existing solutions in lowpower charger and adapter applications. Its core controller is optimized for CV/CC
charging applications with minimal external parts count and very tight control of both the
output voltage and current, without the use of an optocoupler. The LNK616PG has an
integrated 700 V switching MOSFET and ON/OFF control function which together deliver
high efficiency under all load conditions and low no-load energy consumption. Both the
operating efficiency and no-load performance exceed all current international energy
efficiency standards.
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The LNK616PG monolithically integrates the 700 V power MOSFET switch and
controller. A unique ON/OFF control scheme provides CV regulation. The IC also
incorporates both output cable voltage-drop compensation and tight regulation over a
wide temperature range for enhanced CV control. The switching frequency is modulated
to regulate the output current for a linear CC characteristic.
The LNK616PG controller consists of an oscillator, a feedback (sense and logic) circuit, a
5.8 V regulator, BYPASS pin programming functions, over-temperature protection,
frequency jittering, a current-limit circuit, leading-edge blanking, a frequency controller for
CC regulation, and an ON/OFF state machine for CV control.
The LNK616PG also provides a sophisticated range of protection features including autorestart for control loop component open/short circuit faults and output short circuit
conditions. Accurate hysteretic thermal shutdown ensures safe average PCB
temperatures under all conditions.
The IC package provides extended creepage distance between high and low voltage pins
(both at the package and PCB), which is required in highly humid environments to
prevent arcing and to further improve reliability.
The LNK616PG can be configured to either be self-biased from the high-voltage DRAIN
pin, or to receive an optional external bias supply. When configured to be self-biased, the
very low IC current consumption ensures a worst-case no-load power consumption of
less than 175 mW at 265 VAC, well within the 300 mW European Union CoC limit. When
fed from an optional bias supply (as in this design), the no-load power consumption
reduces to <50 mW.
The EE16 transformer bobbin in this design provides extended creepage to meet safety
spacing requirements.
This document contains the power supply specifications, schematic, bill of materials,
transformer specifications, and typical performance characteristics for this reference
design.
Page 5 of 40
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Symbol
Min
Typ
Max
Units
Comment
VIN
fLINE
PNL
85
47
265
64
50
VAC
Hz
mW
2 Wire no P.E.
50/60
VOUT
VRIPPLE
IOUT
RCBL
POUT
4.75
900
5.00
150
1000
0.3
5
5.25
1100
V
mV
mA
VNP
INP
PNP
5
900
4.5
V
mA
W
74
ESV1.1
64
ESV2
67
5%
20 MHz bandwidth
10%
6 ft, 24 AWG
Measured per Energy Star Test Method for Calculating the Energy
Efficiency of Single-Voltage External AC-DC and AC-AC Power
Supplies (August 11, 2004).
ESV1:(0.09 ln(PNP)+0.5
ESV2:(0.075 ln(PNP)+0.561
Environmental
Conducted EMI
Safety
>10 dB margin
Line Surge
Differential
Common Mode
1
2
ESD
Ambient Temperature
TAMB
kV
kV
-15
15
kV
40
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3 Schematic
Page 7 of 40
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4 Circuit Description
This circuit uses the LNK616PG in a primary-side regulated flyback power-supply
configuration.
4.1 Input Filter
The AC input power is rectified by diodes D1 through D4. The rectified DC is filtered by
the bulk storage capacitors C1 and C2. Inductors L1 and L2, with capacitors C1 and C2,
form pi () filters to attenuate conducted differential-mode EMI noise. This configuration,
along with Power Integrations transformer E-shield technology, allows this design to
meet EMI standard EN55022 class B with good margin and without a Y capacitor. The
transformer construction also gives very good EMI repeatability. Fusible resistor RF1
provides protection against catastrophic failure. It should be rated to withstand the
instantaneous dissipation when the supply is first connected to the AC input (while the
input capacitors charge) at VACMAX. This means choosing either an over-sized metal-film
or a wire-wound type. This design uses a wire-wound resistor for RF1.
4.2 LNK616PG Primary
The LNK616PG device (U1) incorporates the power switching device, oscillator, CV/CC
control engine, and startup and protection functions all on one IC. Its integrated 700 V
MOSFET allows sufficient voltage margins in universal input AC applications, including
extended line swells. The device is self-powered from the BYPASS pin via the decoupling
capacitor C4. The value of C4 also programs the cable-drop voltage compensation. In
this case, a 1 F capacitor gives the 350 mV (7% of VNO) compensation needed for the
nominal 24-AWG cable, with 0.3 impedance, used in this design. The optional bias
circuit consisting of D6, C5, and R7 increases efficiency and reduces no-load input
power.
The rectified and filtered input voltage is applied to one end of the transformer (T1)
primary winding. The other side of the transformers primary winding is driven by the
internal MOSFET of U1. An RCD-R clamp consisting of D5, R3, R4, and C3 limits drainvoltage spikes caused by leakage inductance. Resistor R4 has a relatively large value to
prevent any excessive ringing on the drain voltage waveform caused by the leakage
inductance. Excessive ringing can increase output ripple by introducing an error in the
sampled output voltage. IC U1 samples the feedback winding each cycle, 2.5 s after
turn-off of its internal MOSFET.
4.3 Output Rectification and Filtering
Transformer T1s secondary is rectified by D7, a Schottky barrier-type diode (chosen for
higher efficiency), and filtered by C7 and C8. In this application, C7 and C8 have
sufficiently low ESR characteristics to allow meeting the output voltage ripple requirement
without adding an LC post filter. Resistor R8 and capacitor C6 dampen high-frequency
ringing and reduce the voltage stress on D7.
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Page 9 of 40
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5 PCB Layout
Notable layout design points are:
1
2
3
4
5
A spark gap and associated slot in the PCB between the primary and secondary
allows successful ESD testing up to 15 kV.
The preferential arcing point routes the energy from ESD discharges back
to the AC input, away from the transformer and primary circuitry.
The trace connected to the AC input side of the spark gap is spaced away
from the rest of the board and its components to prevent arc discharges to
other sections of the circuit.
The drain trace length has been minimized to reduce EMI.
Clamp and output diode loop areas are minimized to reduce EMI.
The AC input is located away from switching nodes to minimize noise coupling that
may bypass input filtering.
Place C4 (the bypass capacitor) as close as possible to the BYPASS pin on U1.
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6 Bill of Materials
Item
1
Qty
1
Ref
Des
C1
C2
3
4
5
6
7
1
1
1
1
2
C3
C4
C5
C6
C7 C8
D1 D2
D3 D4
D5
9
10
1
1
D6
D7
11
12
13
14
15
16
17
18
19
20
21
22
23
2
1
2
2
1
1
1
1
1
1
1
1
1
J1 J2
J3
L1 L2
R1 R2
R3
R4
R5
R6
R7
R8
R9
RF1
T1
24
25
Description
4.7 F, 400 V, Electrolytic, (8 x 11.5)
Mfg
Taicon
Corporation
Ltec
TYD2GM100G13O
Kemet
Panasonic
Murata
Panasonic
Nippon ChemiCon
Vishay
C0805C102KDRACTU
ECJ-2FB1E105K
GRM21BR61C106KE15L
ECJ-2VB1H222K
EKZE100ELL471MHB5D
Diode Inc.
Vishay
LL4148-13
SL44-E3/57T
Keystone
CUI Inc
Tokin
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Vitrohm
Santronics
Ice Components
Precision, Inc
5012
CA-2184
SBC1-152-181
ERJ-8GEYJ103V
ERJ-6GEYJ474V
ERJ-8GEYJ301V
ERJ-3EKF1472V
ERJ-3EKF9761V
ERJ-3GEYJ622V
ERJ-6GEYJ101V
ERJ-6GEYJ122V
CRF253-4 10R
SNXR1346
TP07161
019-6120-00R
U1
Power
Integrations
LNK616PG
J3
JST Sales
America Inc.
HER-2
Page 11 of 40
1N4007-E3/54
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7 Transformer Specification
7.1
Electrical Diagram
7.2
Electrical Specifications
Electrical Strength
3000 VAC
Primary Inductance
Resonant Frequency
Primary Leakage
Inductance
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7.3
Materials
Item
Description
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
7.4
8
10
WD5:
7T 22TIW
WD4:
6T 4x30AWG
WD3:
6T 4x30AWG
3
5
1
35T 35AWG
WD2:
35T 35AWG
35T 35AWG
2
WD1:
NC
15T 3x35AWG
The highlighted 1 mm tape margin (in yellow above) was added to improve consistency in
EMI performance in production. The spacing of the first two layers of the primary winding
improves the effect of the subsequent shield windings and makes the transformer design
less sensitive to winding variations. However, if the transformer can be manufactured
consistently to comply with EMI performance specifications without the extra margin tape,
omit the margin tape to reduce transformer cost and increase the wire gauge of the
primary winding so that each layer fills the bobbin window width in 35 turns.
Page 13 of 40
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7.5
25-Nov-08
Transformer Construction
Bobbin Preparation
Primary side of the bobbin is placed on the left hand side, and secondary side of
the bobbin is placed on the right hand side.
WD1
Shield
Temporarily hang the start end of the wires of item [3] on pin 7, wind 15 tri-filar
turns from right to left with tight tension and evenly. The maximum allowed gap
between the winding and the left and right lateral walls of the bobbin must be
less than 0.5 mm (20 mils). Cut the end of the wire and bring the start end of the
wire across the bobbin to the left to terminate at pin 2.
Insulation
WD2
Primary
Insulation
WD3
st
1 half Bias
Insulation
2
nd
WD4
half Bias
Insulation
WD5
Secondary
Start pin 10, wind 7 turns of item [5] from right to left uniformly, at the last turn
bring the wire across the bobbin to the right side to terminate at pin 8. Cut three
pins from the secondary side: 6, 7, and 9.
Insulation
Finish
Grind the core to get 1.074mH. Secure the core with tape. Dip vanish [9].
Note:
1. Tape between adjacent primary winding layers reduces primary capacitance and losses.
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8 Design Spreadsheet
RD-158 Power
Integrations
INPUT
INFO
OUTPUT
5.00
0.70
0.50
tC
Add Bias Winding
YES
CIN
14.7
3.00
YES
UNIT
ACDC_LinkSwitch-II_040108_Rev1-0.xls;
LinkSwitch-II Discontinuous Flyback
Transformer Design Spreadsheet
V
V
Hz
V
A
ms
uF
LNK616
PG
0.39
0.41
0.45
67.25
A
A
A
kHz
VOR
82.50
VDS
10.00
VD
0.50
KP
2.31
6.00
4.71
5.00
V
V
9.00
NB
Page 15 of 40
6.00
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DESIGN PARAMETERS
DCON
4.5
TON
4.50
4.31
us
us
RUPPER
RLOWER
12.88
9.16
k-ohm
k-ohm
25-Nov-08
87.45
374.77
V
V
A
A
A
A
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2200.00
2184.51
nH/turn
^2
Gauss
Gauss
BP
2643.26
Gauss
BAC
1092.26
Gauss
ur
LG
BWE
OD
165.37
0.25
25.80
0.25
mm
mm
mm
BM_TARGET
BM
87.68
2200
INS
0.05
DIA
AWG
0.20
33.00
CM
50.80
CMA
362.53
mm
23.00
568.02
PIVS
29.98
Note: Different spreadsheet revisions may give slightly different spreadsheet values.
Page 17 of 40
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9 Performance Data
All measurements were taken at room temperature unless otherwise specified, with
60 Hz input frequency. Measurements were taken at the end of a 6 ft, 0.3 , 24 AWG
output cable.
9.1
Efficiency
85%
Vin=85 VAC
Vin=115 VAC
Vin=230 VAC
Vin=265 VAC
Efficiency
80%
75%
70%
Energy Star v2 Average Active Mode Efficiency (67%)
65%
Energy Star v1.1 / CEC (2008) Average Active Mode Efficiency (64%)
60%
0
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% of Full Load
Efficiency (%)
115 VAC
230 VAC
25
74.8
74.0
50
75.0
74.7
75
73.5
74.4
100
72.2
73.5
Average
73.9%
74.2%
64%
67%
64%
67%
<1W
1 W to 49 W
> 49 W
0.5 PNP
0.09 ln (PNP) + 0.5 [ln = natural log]
0.84
All
0.5 W
For single-input voltage adapters the measurement is made at the rated (single) nominal
input voltage only (either 115 VAC or 230 VAC). For universal input adapters, the
measurement is made at both nominal input voltages (115 VAC and 230 VAC).
To meet the standard, the measured average efficiency (or efficiencies for universal input
supplies) must be greater than or equal to the efficiency specified by the CEC/Energy
Star v1.1 standard.
Page 19 of 40
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1W
> 1 W to 49 W
> 49 W
0.87
0 to <50 W
50 to 250 W
0.3 W
0.5 W
Low-voltage Models
A low-voltage model is an external power supply (EPS) with a nameplate output voltage
of less than 6 V and a nameplate output current greater than or equal to 550 mA.
Nameplate Output (PNP)
1 W
>1 W to 49 W
>49 W
0 to <50 W
50 to 250 W
0.3 W
0.5 W
For the latest up-to-date information, please visit the PI Green Room at
www.powerint.com.
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9.3
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
50
100
150
200
250
300
Page 21 of 40
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9.4
25-Nov-08
Regulation
5
Minimum Limit
85 VAC, 40 Deg C
230 VAC, 40 Deg C
85 VAC, 25 Deg C
230 VAC, 25 Deg C
85 VAC, 0 Deg C
230 VAC, 0 Deg C
Maximum Limit
115 VAC, 40 Deg C
265 VAC, 40 Deg C
115 VAC, 25 Deg C
265 VAC, 25 Deg C
115 VAC, 0 Deg C
265 VAC, 0 Deg C
0
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
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6
0 C External Case Ambient
Minimum Limit
Maximum Limit
85 VAC
115 VAC
230 VAC
265 VAC
0
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
5.5
5.4
5.3
Minimum Limit
Maximum Limit
85 VAC
115 VAC
230 VAC
265 VAC
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
Typical CV/CC Characteristic Over Line at 0 C. Expanded View, Illustrating Effect of Cable
Drop Compensation.
Page 23 of 40
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6
25 C External Case Ambient
Minimum Limit
Maximum Limit
85 VAC
115 VAC
230 VAC
265 VAC
0
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
5.3
Minimum Limit
Maximum Limit
85 VAC
115 VAC
230 VAC
265 VAC
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
Page 24 of 40
25-Nov-08
6
40 C External Case Ambient
85 VAC
115 VAC
230 VAC
265 VAC
Minimum Limit
Maximum Limit
0
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
5.3
85 VAC
115 VAC
230 VAC
265 VAC
Minimum Limit
Maximum Limit
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
Page 25 of 40
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10 Thermal Performance
10.1 Operating Temperature Survey
Thermal performance was measured inside an enclosure at full load with no airflow. A
thermocouple was attached to U1s source pin.
Item
85 VAC
Ambient
40 C
U1 Source Pin
97 C
115 VAC
40 C
90.7 C
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175 VAC
0
40 C
0
89.3 C
230 VAC
0
40 C
0
90.6 C
265 VAC
0
40 C
0
93.1 C
Page 26 of 40
25-Nov-08
11 Waveforms
11.1 Drain Voltage and Current, Normal Operation
Page 27 of 40
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C1
10,000 uF
35 V
Page 29 of 40
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Probe Ground
Probe Tip
Figure 29 Oscilloscope Probe Prepared for Ripple Measurement (End Cap and Ground Lead Removed).
Figure 30 Oscilloscope Probe with Probe Master 4987BA BNC Adapter (Modified with Wires for Probe
Ground for Ripple measurement and Two Parallel Decoupling Capacitors Added).
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Page 33 of 40
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12 Line Surge
Differential input line 1.2 s / 50 s surge testing to IEC61000-4-5 standards was
completed on a single test unit. The input voltage was set at 230 VAC / 60 Hz. The output
current was 1 A and operation was verified following each surge event.
Surge
Level (V)
+500
-500
+750
-750
+1000
-1000
Page 35 of 40
Input
Voltage
(VAC)
230
230
230
230
230
230
Injection
Location
Injection
Phase ()
Test Result
(Pass/Fail)
L to N
L to N
L to N
L to N
L to N
L to N
90
90
90
90
90
90
Pass
Pass
Pass
Pass
Pass
Pass
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13 Conducted EMI
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Page 36 of 40
25-Nov-08
Power Integrations
29.Jan 08 11:11
RBW
MT
9 kHz
500 ms
Marker 1 [T1 ]
43.60 dBV
673.936068749 kHz
10 MHz
PASS
100 MHz
Att 10 dB AUTO
dBV
1 MHz
80
LIMIT CHECK
70
1 QP
CLRWR
EN55022Q
2 AV
CLRWR
EN55022A
SGL
60
TDF
50
1
40
30
6DB
20
10
-10
-20
150 kHz
MEI
100 MHz
Date: 29.JAN.2008
11:11:11
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Power Integrations
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25-Nov-08
14 Revision History
Date
15-May-08
25-Nov-08
Author
JAC
SF
Revision
1.0
1.0
Power Integrations
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Reviewed
JD
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Power Integrations
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25-Nov-08
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