Lab Report: Eee454 Vlsi I Group No
Lab Report: Eee454 Vlsi I Group No
Lab Report: Eee454 Vlsi I Group No
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VLSI I
Group No
Prepared by:
Student Name: Purab Ranjan Sutradhar
Student ID: 1106054
Name(s) of Group Member: Md. Hasibul Hasan
Student ID of Group Member 1106062
Date of Experiment: 05-03-2016
Date of Report: 02-04-2016
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ABSTRACT
Digital electronic circuits are based on some basic solid state transistor amplifier devices which have very
distinctive characteristics and hence very well formed mathematical models. This enables us to incorporate
digital simulation to approximate these devices nature and use it to design electronic circuits. Thus comes the
computer based circuit simulation programme known as SPICE. This experiment aims at familiarizing SPICE
simulation by introducing to the learners how to design the basic building block of modern electronic circuit,
called CMOS using a spice simulation software.
1.
Inverter
KEYWORDS:
2. CMOS
3. Pull-down
4. Pull-up
5.
Low-pass Filter
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TABLE OF CONTENTS
Page
Abstract......................................................................................................2
Keywords:...................................................................................................2
TABLE OF CONTENTS................................................................................3
Introduction...............................................................................................4
Theory.........................................................................................................4
Pre-Work Data and Results.........................................................................4
Lab Handout Questions...............................................................................4
Tools used...................................................................................................9
PROCEDURE...............................................................................................9
Results........................................................................................................9
Conclusion .................................................................................................9
References..................................................................................................9
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INTRODUCTION
This experiment incorporates following features:
# Computer based SPICE simulation of the basic block of electronic circuitry called CMOS.
# Circuits containing resistors, capacitors, inductors, voltage sources, MOSFET analyzed.
# Non-linear transient, linear ac analysis and other types of simulations performed.
THEORY
To simulate the performance of a circuit, using SPICE software the various nodes
are given a unique name. The circuit can be simulated in SPICE by a set of program
statement stored in data file. A typical input consists of a title line, a set of element
statements that describe the circuit and a set of control statements that instruct SPICE
during program execution. the file must then end by an. END control statement. The
lines starting with asterisk (*) are considered comment line.
LAB HANDOUT QUESTIONS
Question-1. Write SPICE source file for the circuit below and produce a transient analysis
the circuit over a period of 1u sec with increment of 10 ns. Determine the rise time
and fall times from the plot.
1 volt
1 Mhz
Answer:
Sourcefile:
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r1 1 2 50
c1 2 0 1n
vin 1 0 pulse(0 1 5ns 1ns 1ns 500ns 1us)
.tran 1ns 2us 0
.probe
.end
Plot:
1.0V
0.5V
0V
0s
0.2us
V(1)
0.4us
0.6us
0.8us
1.0us
1.2us
1.4us
1.6us
1.8us
2.0us
V(2)
Time
Vout
Mpd
Cload
(a)DC Analysis:
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Sourcefile:
mpd 2 1 0 0 nenh l=3u w=4u
mpu 2 1 3 3 penh l=3u w=10u
.model nenh nmos level=2 vto=0.85 kp=30e-6 tox=470e-10 nsub=38e14
+ld=0.6e-6 uo=624 uexp=.055 vmax=20e4 neff=9.8 delta=2
+cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=.33 pb=.81
.model penh pmos level=2 vto=-0.85 kp=12e-6 tox=470e-10 nsub=8.7e14
+ld=0.5e-6 uo=200 uexp=.18 vmax=12e4 neff=4 delta=2
+cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=.33 pb=.7
cl 2 0 50f
vin 1 0 dc 5v
vdd 3 0 dc 5v
.dc vin 0 5 .1
.probe
.end
Plot:
Transient Analysis:
Sourcefile:
mpd 2 1 0 0 nenh l=3u w=4u
mpu 2 1 3 3 penh l=3u w=10u
.model nenh nmos level=2 vto=0.85 kp=30e-6 tox=470e-10 nsub=38e14
+ld=0.6e-6 uo=624 uexp=.055 vmax=20e4 neff=9.8 delta=2
+cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=.33 pb=.81
.model penh pmos level=2 vto=-0.85 kp=12e-6 tox=470e-10 nsub=8.7e14
+ld=0.5e-6 uo=200 uexp=.18 vmax=12e4 neff=4 delta=2
+cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=.33 pb=.7
cl 2 0 50f
vin 1 0 pulse(0 5 3ns 3ns 3ns 20ns 40ns)
vdd 3 0 dc 5v
.tran 1ns 80ns 0
.probe
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.end
Plot:
6.0V
4.0V
2.0V
0V
-2.0V
0s
V(2)
5ns
V(1)
10ns
15ns
20ns
25ns
30ns
35ns
40ns
45ns
50ns
55ns
60ns
65ns
70ns
75ns
80ns
Time
(b)
From the plot, rise time, tr=1.9217 ns
fall time, tf= 1.3377 ns
4.0V
(2.3771,2.3724)
2.0V
0V
0V
0.5V
V1(cl)
1.0V
1.5V
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
vin
vin
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6.0V
4.0V
2.0V
0V
0V
0.5V
V1(cl)
1.0V
1.5V
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
vin
vin
TOOLS
USED
PSPICE AD basics, version 9.2 by Cadence Design Systems inc.
PROCEDURE
1. Label the nodes of the circuit clearly
2. The ground node must be zero
3. Write the circuit description and control statements in a text file and save it with an .cir
extension
4. Simulate
5. Observe the desired values in the probe window.
RESULTS
For Wn =4um, Ln=3um, Wp =10um, Lp=3um,
Rise time, tr =1.9217 ns
fall time, tf= 1.3377 ns
Inversion voltage, Vinv= 2.37 V
For Wn =4um, Ln=3um, Wp =4um, Lp=3um,
Rise time, tr =3.382ns
fall time, tf= 1.4684 ns
Inversion voltage, Vinv= 1.99 V
CONCLUSION
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1.
The CMOS inverter circuit works best when the NMOS and PMOS are fully symmetrical that
means when
width to length ratio of the PMOS is approx. 3 times the width to length ratio of NMOS.
2. When n> p the DC transfer curve moves to the left and when n<p it moves to the right.
3. Rise time depends on p . So for smaller rise time W/L ratio of PMOS should be increased.
4. Fall time depends on n. So for smaller rise time W/L ratio of NMOS should be increased.
5. The smaller the rise time the lower the short circuit power dissipation.
6. The noise margins should be as high as possible and the best possible case is when low
noise- margin and high noise margin are equal.
References
1. Douglas A. Pucknell, Basic VLSI Design , Chapter 2, section 10, Third Edition, PHI .
2. studentnet.cs.manchester.ac.uk, CMOS ,University of manchester , 2015.