10CS33:LOGIG DESIGN

QuestionBank:
Unit 1: Digital Principles and Applications
1. Explain analog and digital signals with examples.
2. Define Period, frequency, Switching time and Duty cycle.
3. Explain the circuit model and operation of the buffer, tri-state buffer, the inverter and the Tristate inverter.
4. Explain standard TTL.
5. Explain the loading rules.
Unit 1: DigitalLogic
1. Explain the logic circuit and truth table of the Inverter, OR gat and AND
gate
2. Why NAND & NOR gates are called universal gates.
3. Differentiate between positive and negative logic.
4. Convert NAND gate into Inverter, in two different ways.
5. What are universal gates? Implement the following function
using universal gates ((A+B)C))D
6. Implement AB+C D with only three NAND gates. Draw logic
diagram also. Assume the inverted input is available.
7. What is assertion level logic?
8. Explain Expander with an example.
Unit 2: Combinational LogicCircuit
1. Minimize the following using K-maps:
i)SOP expression given by f(A,B,C,D) = m(0,1,2,3,5,9,14,15) +
(4,8,11,12)
ii)POS expression given by f(A,B,C,D) = M(0,1,2,5,8,9,10)
2. Implement the minimal expressions thus obtained using
basic gates(both normal and inverted inputs can be used)
3. List out the difference between combinational and sequential logic
circuits.
4. Demonstrate by means of Truth table the validity of following
theorem of Boolean algebra.
i) Associative law
ii) Demorgan's law for Validity
iii) Distributive law
5. Simplify the following Boolean function to minimum no. of literals.
i) xy+xy1 ii) (x+y) (x+y1)
iii)
xyz+x1y+xyz1
iv) y(wz1+wz)+xy v) (A+B)1
((A1+B1)1
6. Reduce the Boolean Expression to required number of literal.
i) BC+AC1+AB+BCD
ii) [(CD1) + A ]1+A+CD+AB
1
1
iii) [(A+C+D) (A+C+D ) (A+C +D) (A+B1)
7. Obtain Truth table for function F=xy+xy1+y1z.
8. Convert the following to other canonical form.

i)

F(x,y,z) =(1,3,7)
ii) F(A,B,C,D)=
(0,2,6,11,13,14)
iii) F(x,y,z)=(0,1,2,3,4,6,12)
9. Show that dual of Exclusive-OR is equal to its complement.
10. Expand the following function into canonical SOP form f(x1,x2,x3)
= x1x3 + x 2 x 3 +
x1x2x3
11. Expand the following function into canonical POS form F(W,X,Q)
=(Q+W1) (X+Q1)
(W+X+Q) (W1+X1)
12. Mention different methods of simplifying Boolean functions.
13. Discuss
K-map &
Quine McCluskey
methods
for
simplification
of
Boolean expressions.
14. Define term Dont care condition.
15. Explain K-map representation in detail & discuss the merits &
demerits.

16. Explain the tabulation procedure in detail & discuss merits &
demerits.
17. Compare K-map & Quine - McClusky methods for
simplification of Boolean
Expression.
18. Obtain the simplified expression in sum of products
for the following: F(A,B,C,D,E) =
(0,1,4,5,16,17,21,25,29)
BDE+B1C1D+CDE+A1B1CE+A1B1C+B1C1D1E1
F(x,y,z)= x1z + w1xy1+w(x1y+xy1)
19. Obtain simplified expression in SOP & POS form
i)
x1z1+y1z1+yz1+xyz ii)
1
1
w yz +vw1z1+vw1x+v1wz+v1w1y1z1
20. and draw gate implementation using AND & OR gates
21. Given the function T(w,x,y,z)=(1,3,4,5,7,8,9,11,14,15).Use
K map to determine the set of all prime-implicants. Indicate
essential prime-implicants,
find three distinct minimal
expressions for T
22. Using tabulation method, determine the set of all prime implicate
for the function
f(w,x,y,z) = (0,1,2,5,7,8,9,10,13,15) and hence obtain the
minimal form of given function, employing decimal notation.
23. Implement the following function with NAND and NOR gates. Use
only four gates.
Only normal inputs are
available. F = W1
xz+W1yz+x1yz1+Wxy1z
D = Wyz
24. Compare K-map
&
QuineMcCluskey methods
for simplification of Boolean
Expression. Give their merits and demerits
25. Using K-map simplify following Boolean expression & give
implementation of same using
i)
NAND gates only
ii) AND,OR & Invert gates for F(A,B,C,D) =(2,4,8,16,31)+
D(0,3,9,12,15,18)
26. Simplify Boolean function by Tabulation method
F(A,B,C,D,E,F,G)= (20,28,52,60)
F(A,B,C,D,E,F,G)= (20,28,38,39,52,60,102,103,127)
27. Give two simplified irredundant expression for F(w,x,y,z)=
(0,4,5,7,8,9,13,15)
28. Determine set of Prime implicants for function F(w,x,y,z)=
(0,1,2,5,7,8,9,10,13,15)
29. Implement following function with NAND & NOR gates. Use only four
gates
F=w1xz+w1yz+x1yz1+wxy1z, d=wxy+wyz
30. Minimize the following function with dont care terms
using Q.M. method f(A,B,C,D)=
m(5,7,11,12,27,29)+d(14,20,21,22,23)
f(A,B,C,D)= m(1,4,6,9,14,17,22,27,28,)+d(12,15,20,30,31)

31. Implement the following function using NAND gates f(X,Y,Z)= (0,6)
32. Implement the following function using NOR gates F(x+y1) (x1+y)z1
33. Determine
the set of
Prime-implicants
for
function F(w,x,y,z)=
(0,1,2,5,7,8,9,10,13,15)
34. Using Quine-Mc Clauskey obtain the set of Prime
implicants for function
F(a,b,c,d,e)= (4,12,13,14,16,19,22,24,25,26,29,30)+
d(1,3,5,20,27)
35. Find the minimal two level NOR realization for each following
function f(A,B,C)=
m(1,4,6,8),
f(A,B,C,D,E)= m(3,5,7,12,23,27,28,30)
36. Find the minimal two level NAND realization for each following
function f(A,B,C)=
m(0,2,3,7)
37. f(A,B,C,D,E)= m(4,5,6,7,25,27,29,31)
38. Prove the following boolean identities:
1. A(B+C)=AB+AC
2. A(A+BC)=A
3. AB+AB+AB=A+B
39. Find minimal sum and minimal product of the
following Boolean function.
f(W,X,Y,Z)=m(0,1,3,7,8,12)+d c(5,10,13,14)
40. Using Quine Mc Cluskey method, determine the prime
applicants of the following function.
f(W,X,Y,Z)=m(7,9,12,13,14,15)+d c(4,11)

41. Simplify the follwing using K-map,

F(A,B,C,D)=(AB)C+AD+BD+CD+AC+(AB)
42. What are the drawbacks of K-map? Simplify the following
expression using Quine- McCluskey method.
F(A,B,C,D)=1,2,8,9,10,12,13,14).
UNIT 3: DataProcessingCircuit
1. W h y i s a M u l ti p l e x e r c a l le d a U n i v e r sa l lo g i c c ir c u i t?
2 . Configure 16 to 1 MUX using 4
to 1 MUX
3. Implement the f(x,y,z) = m ( 0,4,5,6) function
using 8 to 1 MUX
4. Implement the f(x,y,z) = m (0,1,2,7 ) function
using 4 to 1 MUX
5. Implement the f( w,x,y,z) = m (0,1,5,6,15,7,10,9 ) function
using 8 to 1 MUX. Treat a, b and c as the select lines.
6. Implement the above function using 4 to 1 MUX with a
and b as select lines.
7.
Implement
the
Boolean function
f( a,b,c,d ) = m
(4,5,7,8,10,12,15) using 4 to 2 MUX and external gates if, a and b
are connected to select lines a1 and a2 respectively, c and d are
connected to select lines a1 and a2 respectively.
8. Implement the following using 3 to 8 decoder with NAND outputs
or active low outputs
F1(a,b,c) = m(1,3,5,6); F2(a,b,c) =
m( 0,2,5,6)
9.
Define parity generator and
parity checker.
10.
Define an excess-3 to 8421 code converter using a 4 to 16
decoder with an enable input
E using NAND gates, so as to minimize
the gate inputs.
11. Using decoder implement the following Logic functions. a. Active
High decoder with OR gate, b. Active Low decoder with NAND gate,
c. Active High decoder with NOR gate, d. Active Low decoder with
AND gate.
12. Design 2-4 decoder with
enable input E.
13. Design 3-8
decoder.
14. Design 4-16
decoder.
15. Mention the application
of decoder.
16. How many outputs a magnitude

comparator generates?
17. Show how two 1 to 16 demultiplexers can be connected to get
1 to 32 demultiplexer.
18. Design a 32 to 1 multiplexer using two 16 to 1 multiplexer and
one 2 to 1 multiplexer.
19. Give seven segment decoder
using PLA.
20. Show that using a 3-to-8 decoder and multi-input OR gate, the
following expressions can be realized. F1(A,B,C)= m(0,4,6);
F2(A,B,C)= m(0,5); F3(A,B,C)= m(1,2,3,7)
21. Design Decimal to BCD
encoder.
22. What are the different types of PLDs and implement the
7-segment decoder.
23. Mention different types of ROMS and explain
each one of them.
24. What are the different models for writing a module body in
Verilog HDL. Give an example for any one model.
25. Realize the Boolean expression f(w,x,y,z)=
m(4,6,7,8,10,12,15) using 4:1 line mux and external gates.
Unit 4: Clock andTimingCircuit
1. Calculate the clock cycle for a system that uses a clock that has a
frequency of a. 10 MHz,
b. 6 MHz c. 750 MHz
2. What is Schmitt trigger? Explain its transfer characteristics and
draw the input and output waveforms.
3.
Determine the frequency of oscillation for the 555 timer given
RA = RB=1K and
C = 1000pF
4.
A sine wave with a peak of 2V drives one of the inverter in
a 7414.sketch the output voltage.
5.
What is a System clock: What are the characteristics of an ideal
clock?
Unit 4: FLIPFLOPSANDSIMPLEFLIPFLOPAPPLICATIONS
1. Mention the difference between combinational & sequential circuits
with block diagram.
2. Mention the difference between asynchronous & synchronous circuits
with example.
3. Differences between Latch & Flip flop give example.
4. Define clocked sequential circuit.
5. Difference between Characteristic & Excitation table.
6. Explain the operation of different types of flip flop.
7. What is Race round condition. Explain.

8. Explain the operation of JK flip-flop. With logic diagram,

characteristic table.
9. Discuss how unstable condition S=R=1 is avoided in storage latch
of the following: a) D
latch b) JK flip flop c) T flip flop
10. Explain clocked RS flip flop with logic diagram.
11. Show that clocked D flip-flop can be reduced by one gate.
12. Explain how D & T flip flop works with logic diagram.
13. Discuss state table, state diagram, and state equation with example.
14. Explain registers.
15. Give a block diagram of sequential circuit employing register
as a part of sequential circuit.
16. What are the applications of flip-flops?
17. How flip-flop will differ from latches?
18. Differentiate between combinational and sequential circuit.
19. Show how to convert a D flip flop into SR flip flop.
20. Explain the working of a JK Master- slave flip flop. Write its
truth table, state diagram and excitation table.
21. Show how to convert a SR flip flop into JK flip flop.
Unit 5: Registers
1. Mention the capabilities of shift register.
2. Explain universal shift register (74194).
3. Design synchronous BCD counter using JK flip flops.
4. Explain how shift register can be used as counters.
5. Mention the difference between ripple & synchronous counters.
6. Discuss shift registers.
7. Discuss state table, state diagram, and state equation with example.
8. Discuss the procedure for designing sequential circuits.
9. Define counter and write state diagram for 3-bit binary counter.
10. Explain registers.
11. Discuss serial transfer of information from one register to other.
12. Give a block diagram of sequential circuit employing register
as a part of sequential circuit.
13. Give logic diagram of 4 bit bi-directional shift register with parallel
capability & briefly
explain its operation.
14. Give logic diagram of 4-bit binary ripple counter & BCD Ripple
counter
15. Construct mod 6 counter using MSI chip.
16. Write the logic diagram of a 4 bit bi-directional shift register with
parallel load capability and explain its operations.
17. Design a 4-bit serial input shift registers in detail and give its timing
diagram.
18. Design a mod-5 synchronous up counter using JK flip flop.
19. Name and explain in short the four basin types of shift
register and draw the block diagram for each.
Unit 6 : Counters

1. How many flip-flops are required to construct a mod-128 counter?

2. What is the largest decimal number that can be stored in a mod 64
Counter?
3. Differentiate between Synchronous and Asynchronous counter.
4. Write a Boolean expression for the And gate connected for the
AND gate Connected to the lower leg of the
OR gate that drives
the clock input to Flip-flop QA in 54/74193.
5. Design a 4-bit ripple counter using negative edge triggered JK flipflop.
6. Design a 4-bit binary ripple counter using positive edge triggered
D-Flip Flop without a count enable line.
7. Design a mod-5 synchronous counter to sequence the first 5
state from 0000 to 0100 and repeat using a 4-bit synchronous
counter with parallel load facility.
8. Explain 4-bit shift register of serial with timing diagram.
9. Explain ripple counter with truth table and waveform.
10. Design a divide by two counter using D-Latch.
11. Distinguish between a ring counter and Johnson counter.
12. Explain the working of a 3-bit asynchronous down counter.
13. Design a synchronous mod-5 up counter using JK flip flop. Give
excitation table. The counter sequence is 0,1,2,0,1,2

Unit 7 Designofsequentialcircuit
1. Explain the structure and operation of Clocked synchronous
sequential networks.
2. What are uses of Transition tables and
Excitation tables?
3.
Write short
notes on
a) Mealy and Moore
Models. b) State
Machine notation
4. Define the
following terms a)
Excitation table
b)
Next state
and
present state
5. Draw Mealy and Moore synchronous machine models. Label
the excitation variables, state variables, input variables, and output
variables in both diagrams
6.
Explain why unused states generate dont-care terms when
translating a state table to a transition table. Illustrate your response
with a sample state table.
7.
Write short
notes on
a) State Diagram and
state table b) Transition
table.
8. Construct a Mealy state diagram that will detect a serial input
sequence of 10110. The detection of the required bit pattern can
occur in a longer data string and the correct pattern can overlap
with another pattern. When the input pattern has been detected,
cause an output z to be asserted high. For example, let the input
string be X = 1 0 1 1 0 1 1 0 1 1
0, Z = 0 0 0 0 1 0 0
10 01
9. Design a cyclic modulo-8 synchronous binary counter using J-K
flip-flops that will count the number of occurrences of an input;
that is, the number of times it is 1. The input variable x must be
coincident with the clock to be counted. The counter is to count
in binary.
10. Construct the state diagram for a Mealy sequential circuit that will
detect the serial input sequence x = 010110. When the complete
sequence has been detected, then cause output z to go high.
11. Construct the state diagram for a Mealy sequential machine that
will detect the following input sequences: x= 01101 or 01111. If input
sequence x = 01101 is met, cause z1 = 1. If x = 01111, cause z2=1.
Each input sequence may overlap with itself or the other sequence.
12. Design a Moore sequential machine state diagram that will

determine whether a four-bit

serial input sequence is a legal 8-4-2-1 BCD code. If a legal BCD code
sequence is detected, then z = 1. If an incorrect code is entered,
then z = 0.
13. Design a decade counter using a binary state assignment and JK flip flops such that when two external inputs (x and y) are
coincident the counter will increment. A separate clock input
provides state transition synchronization.
14. Draw state transition diagram of sequence detector circuit that
detects 1101 from the input data stream using both Mealay and
Moore model.
15. Reduce the state transition diagram by row elimination and
implication method and implication table method.

16. Draw an ASM chart for a 2 bit counter having one enable line
such that E=1 (counting enabled) E=0 (counting disabled). Reduce
state transition diagram (Moore model) of fig by i) Row elimination
method. Ii) Implication table method

Unit 8: D/AConversionandA/Dconversion
1. Find the binary weight of each bit in a 4-bit system.
2. What are the output voltages caused by each bit in a 5-bit ladder if
the input levels are
0=0 v and 1 = +10v
3. How many bits are required in a binary ladder to achieve a
resolution of 1 mV if full scale is +5V
4. Find the following for a 12-Bit counter type A/D converter
using 1-MHz clock: a. Maximum conversion time, b. Average
conversion time and c. Maximum conversion rate.
5. What is the conversion time of a 12-bit section-counter-type
A/D Converter using 1 MHz clock? The counter is divided into three
parts.
6. What is a monotonicity test?
7. What is the resolution of a 9-bit D/A converter which uses 9
ladder networks? What is the resolution expressed as a percent? If
the full-scale output voltage of this converter is
+5v? What is the resolution in volts?

8. Explain with the block diagram of successive approximation ADC.

9. What is a binary ladder? Explain the binary ladder with digital input
of 1000.
10. Explain accuracy and resolution for ADC.
11. Explain a 2-bit simultaneous A/D converter. Draw the block diagram
of the same.
12. Explain continuous A/D converter with an example.