Karpagam University

Digital Labs
Revision 2.0
Incisive Unified Simulator 9.2
RTL Compiler 9.1
Encounter Digital Implementation 9.1

Developed by,
University Support Team
Cadence, Bangalore

Table of Contents
General Notes...................................................................................................................... 3
Lab1: An Inverter ................................................................................................................ 4
Lab 2: A Buffer ................................................................................................................... 7
Lab 3: Transmission Gate ................................................................................................. 12
Lab 4: Basic / Universal Gates.......................................................................................... 19
Lab 5: Flip-Flops............................................................................................................... 25
Lab6: NCO(10 Bit number controlled oscillator) ............................................................. 30
mem.v mux_2to1.v phase_inc.v testbench.v top.v ............................................... 31
Lab7: Automatic layout generation followed by post layout extraction and simulation of
the circuit studied in Lab 6................................................................................................ 38

General Notes
There are a number of things to consider before beginning these lab exercises. Please
read through this section completely, and perform any needed steps in order to ensure a
successful workshop. These labs were designed for use with Incisive Unified Simulator.

Before running any of these labs, ensure that youve set up IUS correctly:
%> setenv IUSHOME <IUS-installation-home>

The Cadence_Digital_labs directory contains Solutions folder and also Work folder.
Inside Work folder you can make modifications of the code locally without affecting
your Source code present inside Solutions directory.
Lab directory details:
. /Solutions

Contains a local copy of all the lab experiments including

Testbences for simulating the codes.

. /Workarea

Its a place to run Simulation and Synthesis.

To setup the lab environment, please perform the following steps:

1. Ensure the software mentioned above is correctly setup.
2. Source the C-Shell related commands file i.e (cshrc file).
These labs were designed to be run using Cadence Simulator and the synthesis engine.

Lab1: An Inverter
In this lab we will simulate the inverter code modeled using switch level by the
help of Incisive unified simulator.In this lab we will see how to perform simulation in
command mode using testbench without using GUI window.
1. Change directory to Cadence_Digital_labs/Workarea/Inverter
2. You will need to copy each file present in solutions folder to Workarea/Inverter
location by using the below mentioned command :

cp -rf ../../Solutions/Inverter/* .
3. View the Code of Inverter and also the testbench for the same.
4. Compile the source Descriptions :
(i) Compile the Inverter description with the -messages option:

ncvlog inverter.v messages

The compiler places the inverter description in the INCA_libs library.

(ii) Compile the testbench description with the -MESS option:

ncvlog inverter_test.v MESS

The compiler places the inverter_test description in the INCA_libs library.

Note: You can abbreviate options down to their shortest unique string and use upper or
Lower case.
List all inverter library objects (ncls inverter).

What library objects does the compiler create?

Answer: The compiler creates Verilog VST objects.
5. Elaborate the top level Design
(i) Elaborate the testbench

ncelab inv_test -messages

The elaborator places the inv_test code and snapshot in the INCA_libs library.

List all inv_test" library objects (ncls inv_test).

What library objects does the elaborator create?
Answer: The elaborator creates SIG (signature), HDLCODE (code),
and SSS (snapshot) objects.

6. Simulate the Top-Level Design

(i) Simulate the testbench:

ncsim inv_test
The simulator displays results similar to the following:

Lab Summary:
In this lab we saw how to compile, elaborate and simulate the tesbench for Inverter
module.

Lab 2: A Buffer
In this lab, you will simulate a design using the Incisive simulator. You will:
* Create the cds.lib and hdl.var files
* Compile, elaborate, and simulate the design and testbench
Perform this lab in the Buffer directory. This directory contains the following files (which
you should briefly examine) describing a simple Buffer and its testbench:
File(s) Description
Buffer.v Buffer code
Buffer_test.v Testbench

1. Change directory to Cadence_Digital_labs/Workarea/Buffer.

2. You will need to copy each file present in solutions folder to Workarea/Buffer
location by using the below mentioned command :

cp -rf ../../Solutions/Buffer/* .
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3. View the Code of Inverter and also the testbench for the same.
4

Set Up the Design Environment

Using your favorite text editor, create the cds.lib file and make the following entries:

Define Buffer_lib ./Buffer.lib

Create the local library directory:

mkdir Buffer.lib
Create the hdl.var file and make the following entry:

Define WORK Buffer_lib

5. Compile the Source Descriptions

(i). Compile the buffer description with the -messages option:

ncvlog buffer.v messages

The compiler places the Buffer description in the Buffer_lib library.

(ii). Compile the testbench description with the -MESS option:

ncvlog buffer_test.v MESS

The compiler places the buffer_test description in the Buffer_lib library.

Note: You can abbreviate options down to their shortest unique string and use
upper or lower case.
List all mux library objects (ncls buffer).

What library objects does the compiler create?

Answer: The compiler creates Verilog VST objects.

6. Elaborate the Top-Level Design

1. Append this line to the hdl.var file:

Define NCELABOPTS messages

2. Elaborate the testbench:

ncelab buf_test
The elaborator places the buffer_test code and snapshot in the Buffer_lib library.

7. Simulate the Top-Level Design

(i) Simulate the testbench:

ncsim buf_test
The simulator displays results similar to the following:

Lab Summary

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In this lab, you simulated a design using the Incisive simulator. You:
* Created the cds.lib and hdl.var files
* Compiled, elaborated, and simulated the design and testbench

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Lab 3: Transmission Gate

In this lab, you will simulate a design using the Incisive simulator. You will:
* Create the cds.lib and hdl.var files
* Compile, elaborate, and simulate the design and testbench
Perform this lab in the TG directory. This directory contains the following files (which
you should briefly examine) describing a simple Transmission gate and its testbench:
File(s) Description
tg.v -- Transmission Gate code
tg_test.v -- Testbench
1. Change directory to Cadence_Digital_labs/Workarea/TG.
2. You will need to copy each file present in solutions folder to Workarea/TG
location by using the below mentioned command :

cp -rf ../../Solutions/TG/* .
3. View the Code of tranmission gate and also the testbench for the same.
4. Set Up the Design Environment
Using your favorite text editor, create the cds.lib file and make the following entries:

Define tg_lib ./tg.lib

Create the local library directory:

mkdir tg.lib
Create the hdl.var file and make the following entry:

Define WORK tg_lib

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5. Compile the Source Descriptions

(i). Compile the transmission gate description with the -messages option:

ncvlog tg.v messages

The compiler places the Transmission Gate description in the tg_lib library.

(ii). Compile the testbench description with the -MESS option:

ncvlog tg_test.v MESS

The compiler places the tg_test description in the tg_lib library.

Note: You can abbreviate options down to their shortest unique string and use
upper or lower case.

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6. Elaborate the Top-Level Design

(i) Append this line to the hdl.var file:

Define NCELABOPTS messages

(ii) Elaborate the testbench:

ncelab trangate_test -access +rwc

The elaborator places the tg_test code and snapshot in the tg_lib library.

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7. Simulate the top level design:

(i)

Simulate the testbench: with gui option:

ncsim trangate_test gui

The -gui option opens the Console and Design Browser windows.
Tour the Graphical Interface
1. Examine the Console window.
a. You can use the Menu Bar to run or step the simulation, set scopes and stops, show
the value of objects, and start other graphical tools.
b. You can use the Tool Bar to run, interrupt, reset, step, or next the simulation, and
shut down the interface or the simulation, or disconnect the simulation.
c. You can use the command line interface to the simulation in the I/O Region.

2. Examine the Design Browser window.

Open an existing Design Browser window or select the Windows new Design
Browser menu item or the Design Browser button.
a. Display the objects of a scope and their value in the Objects List pane (Select any
displayed scope in the Scope Tree pane).
b. Display the component instances of the scope (double-click the scope in the Scope
Tree pane).

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3. Tour the Waveform window.

Open an existing Waveform window or select the Windows - New - Waveform
menu item or the Waveform
button.The simulator creates a default SHM
database and sets a probe onany selected signals and opens a Waveform window
displaying the selected signals.
a. In the Design Browser window select all signals at the trangate_test scope.
b. Add the selected signal(s) to the Waveform window (select the Waveform button
or the Add Selected button or drag and drop the signals into the Waveform
window).Note: To add additional signals simply select them in any window and
click the Waveform button again.

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Examine the Design and Testbench Hierarchy

In this section of the lab you visit the Source Browser, Schematic Tracer and
Waveform window.
1. In the Design Browser window select the top-level (mem_test) scope and select the
Source Browser
button to send it to the target Source Browser window. As no such
window yet exists, this opens a Source Browser window displaying the source of the
Top-level unit, and makes it the default Source Browser target window.
2. In the Source Browser window ensure that just the top-level scope is selected (navigate
to the target Schematic Tracer
up as needed and SelectThis Scope) and send it
window. As no such window yet exists, this opens a Schematic Tracer window
displaying the top-level unit, and makes it the default Schematic Tracer target window, in
which you:
button,
a. Ensure that the top-level scope is still selected, and select the fill Module
to display the testbench content.
b. Select the Edit - Select - All menus item, and again select the fill Module button, to
Expand the second level content.
c. Select the Zoom Full

button to fit all displayed elements.

3. In the Source Browser window ensure that just the top-level scope is selected and send
it
tothe target Waveform window. As no such window yet exists, this opens a
Waveform window displaying the signals of the top-level unit, and makes it the default
Waveform target window.
a. In the left sidebar, select the Design Browser
display the embedded Design Browser.

tab toexpand the sidebar area and

--- Run the simulation until the next breakpoint, or for the
Duration entered in the time field (i.e 40ns).
--- Current Time range.
--- Move primary cursor to previous edge of select signal.

--- Reset the simulation back to time 0 .

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Once the simulation is done you can see the following waveform window and console
window with the outputs.

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Lab 4: Basic / Universal Gates

In this lab, you will simulate a design using the Incisive simulator. You will:
* Create the cds.lib and hdl.var files
* Compile, elaborate, and simulate the design and testbench
Perform this lab in the Gates directory. This directory contains the following
subdirectories (which you should briefly examine) describing a simple basic/universal
gates and its testbench:
Subdirectories Descriptions:
AND , NAND , NOR , OR , XOR , XNOR
1

Change directory to Cadence_Digital_labs/Workarea/Gates.

You will need to copy each file present in Solutions folder to Workarea/Gates
location by using the below mentioned command :

cp -rf ../../Solutions/Gates/* .
3

Change directory to AND folder.

View the Code of AND gate and also the testbench for the same.

5. This procedure is same for all the other logic gates present inside Gates folder.

6. Set Up the Design Environment

Using your favorite text editor, create the cds.lib file and make the following entries:

Define and_lib ./and.lib

Create the local library directory:

mkdir and.lib
Create the hdl.var file and make the following entry:

Define WORK and_lib

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7. Compile the Source Descriptions

(i). Compile the transmission gate description with the -messages option:

ncvlog and.v messages

The compiler places the And Gate description in the and_lib library.

(ii). Compile the testbench description with the -MESS option:

ncvlog and_test.v MESS

The compiler places the and_test description in the and_lib library.

Note: You can abbreviate options down to their shortest unique string and use
upper or lower case.

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8. Elaborate the Top-Level Design

(i) Append this line to the hdl.var file:

Define NCELABOPTS messages

(ii) Elaborate the testbench:

ncelab andgate -access +rwc -MESS

The elaborator places the andgate code and snapshot in the and_lib library.

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7. Simulate the top level design:

(ii)

Simulate the design: with -gui option:

ncsim andgate gui

Simvision tool from Cadence Design Systems automatically pops up:

The -gui option opens the Console and Design Browser windows.

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Selcet the input and output ports as shown above and click
waveform window.

button to open up the

Select in1 and go to Simulation tab and selcet Create Force option

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Following Create force window comes up .Now apply binary input logic to in1from the
available binary logic 0,1,X,Z.Selcet any logic and click Ok.

In the same way apply another input in2.

Once the inputs are applied, select the time range for simulation and run the simulation
using the following Icon

Output Waveform is as shown below for AND gate :

Its also possible to reset the simulation with this button.

Once the reset is done and want to perform simulation with another set of inputs ,then
follow the same procedure as mentioned ablove.

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Lab 5: Flip-Flops
In this lab, you will simulate a design using the Incisive simulator. You will:
* Create the cds.lib and hdl.var files
* Compile, elaborate, and simulate the design and testbench
Perform this lab in the Flipflops directory. This directory contains the following files
(which you should briefly examine) describing a Flipflops and its testbenches:
File(s) Description:
SR_ff.v

d_ff.v

jk_ff.v

ms_ff.v

t_ff.v

1. Change directory to Cadence_Digital_labs/Workarea/Flipflops

2: You will need to copy each file present in Solutions folder to Workarea/Flipflops
location by using the below mentioned command :

cp -rf ../../Solutions/Flipflops/* .
3. View the Code of SR-Flipflop and also the testbench for the same.
4. This procedure is same for all the other flipflops present inside Flipflops folder.
5. Set Up the Design Environment
Using your favorite text editor, create the cds.lib file and make the following entries:

Define ff_lib ./ff.lib

Create the local library directory:

mkdir ff.lib
Create the hdl.var file and make the following entry:

Define WORK ff_lib

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6. Use the following command to invoke user friendly GUI:

nclaunch &
Following windows appears.This is the GUI of nclaunch.
Rightside of window has ff_lib (worklib ) and snapshots directories listed.
ff_lib is the directory where all the compiled codes are stored while snapshot will have
output of elaboration which in turn goes for simulation.

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Once the above window appears select the flipflop of your choice for ex: I am selecting
SR-ff.v .Once the flipflop is selected click the following buttons shown below for
compilation, elaboration and simulation.
-- This Icon is for compiling the verilog code, once the compilation is done it
Creates VST and you can see SR_ff and SR_ff_test under ff_lib directory.
-- Select SR_ff_test Icon to elaborate the testbench ,once the elaboration is done
It creates snapshot and stores inside snapshots directory.
-- Select the snapshot ff_lib.SR_ff_test: module and click the following Icon to
Invoke the waveform window (Simvision) for performing the simulation.

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Once the Design browser window ( i.e Simvision ) comesup select SR_ff_test also the
required inputs and outputs ports and click the

button to open the waveform window.

Waveform window appears as shown below:

Run the testbech simulation by clicking the following icon

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We will obtain the required output of SR Flip flop in the waveform window as shown
below:

The equivalent command terminal output can be observed in the Simvision console
window and also in the nclaunch console terminal.The o/p is as shown below:

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Lab6: NCO(10 Bit number controlled oscillator)

There are a number of things to consider before beginning the lab exercises. Please
read through this section completely, and perform any needed steps in order to ensure a
successful workshop.

The NCO directory contains rclabs folder. Inside rclabs folder you will see many
other directories but for IUS, change the directory to Simulation and for Synthesis and
P&R select work directory
Lab directory details:
Simulation

Contains the lab experiments including

Testbences for simulating the codes.

work

Its a place to run Synthesis and P&R for NCO.

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In this lab, you will simulate the design using the Incisive simulator. You will Perform
this lab in the Simulation directory. This directory contains the following files (which you
should briefly examine) describing the NCO and its testbenches:
File(s) Description:

mem.v mux_2to1.v phase_inc.v testbench.v top.v

Compile , Elaborate and Simulate using Irun Utility:
Run the below command
irun mem.v mux_2to1.v phase_inc.v testbench.v top.v access +rwc mess gui
1. Now the Console & Design Browser window opens
2. Before proceeding to the next step analyze the messages in the terminal window
The -gui option opens the Console and Design Browser windows.
Tour the Graphical Interface
1. Examine the Console window.
a. You can use the Menu Bar to run or step the simulation, set scopes and stops, show
the value of objects, and start other graphical tools.
b. You can use the Tool Bar to run, interrupt, reset, step, or next the simulation, and
shut down the interface or the simulation, or disconnect the simulation.
c. You can use the command line interface to the simulation in the I/O Region.

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2. Examine the Design Browser window.

Open an existing Design Browser window or select the Windows new Design
Browser menu item or the Design Browser button.
a. Display the objects of a scope and their value in the Objects List pane (Select any
displayed scope in the Scope Tree pane).
b. Display the component instances of the scope (double-click the scope in the Scope
Tree pane).

3. Tour the Waveform window.

Open an existing Waveform window or select the Windows - New - Waveform
button.The simulator creates a default SHM
menu item or the Waveform
database and sets a probe onany selected signals and opens a Waveform window
displaying the selected signals.
a. In the Design Browser window select all signals at the testbench scope.
b. Add the selected signal(s) to the Waveform window (select the Waveform button
or the Add Selected button or drag and drop the signals into the Waveform
window).Note: To add additional signals simply select them in any window and
click the Waveform button again.

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Examine the Design and Testbench Hierarchy

In this section of the lab you visit the Source Browser, Schematic Tracer and
Waveform window.
1. In the Design Browser window select the top-level (mem_test) scope and select the
Source Browser
button to send it to the target Source Browser window. As no such
window yet exists, this opens a Source Browser window displaying the source of the
Top-level unit, and makes it the default Source Browser target window.
2. In the Source Browser window ensure that just the top-level scope is selected (navigate
to the target Schematic Tracer
up as needed and SelectThis Scope) and send it
window. As no such window yet exists, this opens a Schematic Tracer window
displaying the top-level unit, and makes it the default Schematic Tracer target window, in
which you:
button,
a. Ensure that the top-level scope is still selected, and select the fill Module
to display the testbench content.
b. Select the Edit - Select - All menus item, and again select the fill Module button, to
Expand the second level content.
c. Select the Zoom Full

button to fit all displayed elements.

3. In the Source Browser window ensure that just the top-level scope is selected and send
tothe target Waveform window. As no such window yet exists, this opens a
it
Waveform window displaying the signals of the top-level unit, and makes it the default
Waveform target window.
a. In the left sidebar, select the Design Browser
display the embedded Design Browser.

tab toexpand the sidebar area and

--- Run the simulation until the next breakpoint, or for the
Duration entered in the time field (i.e 40ns).
--- Current Time range.
--- Move primary cursor to previous edge of select signal.

--- Reset the simulation back to time 0 .

33

Once the simulation is done you can see the following waveform window and console
window with the outputs.

Further follow the following steps:

1. Highlight the output pin(data_out[5:0]) and right click on it
2. Click on Trace and select Analog/Sample+Hold

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3. Now select the symbol which is highlighted by red circle

35

. Now we can see based on the numerical value (hexadecimal) corresponding

output wave form can be seen.

36

6. Drag and observe the waveform for different numerical values

37

Lab7: Automatic layout generation followed

by post layout extraction and simulation of
the circuit studied in Lab 6
In this lab we will do the Synthsesis and Physical Design of NCO Design for which
simulation is done in Lab6. Synthesis will be done using RTL Compiler and Physical
Design will be done using Encounter Digital Implementation System.
Go to directory /NCO/rclabs/work.
Lets do the Synthesis first.
1. Invoke RTL Compiler by typing rc -gui on your terminal window.
The below picture can be seen after typing the above command.

The tool window look like the below image:

38

The terminal will look like the below image after the tool is invoked.

2. Give the path of the library w.r.t to the directory you are in using the command:
set_attribute lib_search_path ../library
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3 Give the path of the RTL files with respect to the directory you are in using the below
command:
set_attribute hdl_search_path ../rtl
4 Read the library from the directory specified in giving the path for the library files in
step 2 using the command:
set_attribute library slow_normal.lib
slow_normal.lib is the name of the library file in the directory library. There is
another library there in that directory with name slow_highvt.lib. Any one of these
two libraries could be used at a time.
5 Read the RTL files from the directory specified in the path in step 3. The RTL files are
in the directory name rtl:
read_hdl {mem.v mux_2to1.v phase_inc.v top.v}.
6 Now Elaborate the design using elaboratecommand.
7 Give the command to see the circuit in Tool window:
The terminal window after the step 7 will look like
The Tool window looks like image on next page

8. Give the standard delay constraints using:

read_sdc ./constraints_top.g.
The terminal window looks like the image on next page.

40

9. Synthesize the circuit using the command:

synthesize -to_mapped -effort medium.
The terminal window and the synthesized circuit in tool window will appear to be as
on next page:

41

42

10. Write the hdl code in terms of library components for the synthesized circuit using the
command:
write_hdl > nco.hdl
nco.hdl is the name of file in which the code gets write.
11. Similarly write the constraint file using
write_sdc > nco.sdc.
12. Timing could be check using report timing.
13. Similarly for Gates report gates.
14. Check area using report area.
15. Check Power dissipation using report power.
After the Synthesis Physical Design can be done by invoking the tool Encounter
Digital implementation.
16. Go to Directory /NCO/rclabs/work.
17. Invoke the tool using encounter or velocity.
The tool starts as below image:

The terminal window and tool window can be seens as similar to images on next page

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44

18. Go the Tool window and click on the File and select Import Design. A new window
will open.

19. Select the verilog files using browse button. A new window Netlist files will open.

45

20. Click on the arrow button and select the verilog File NCO_gatelevel_uniq.v and
click the Add button and then click the close button.

21. Click on Auto assign after top cell.

22. Similarly select the lef file by clicking the browse button and then add the lef file
with name all.lef in the lef directory.
23. Select the timing libraries. For maximum timing libraries select all libraries with
slow in their name and for minimum timing libraries select all libraries with fast in
their names. Alternatively, instead of selecting all the libraries for Maximum timing
libraries, type ../lib/*slow*.lib in space in front of Maximum Timing Libraries. This
will select all the slow libraries. Similarly in front of Minimum Timing Libraries write
../lib/*fast*.lib.
24. Similarly select NCO.sdc for timing constraint file.
The Design Import window will look like the image on next page:

46

25. In the Design Import window click on Advanced Tab. Select Power out of the list on
the left side of window. Enter the power nets as VDD and Ground nets as VSS.

47

26. Select OK. The tool window will look like image on next page.

48

The pink colour blocks are the standard cells. This is floorplan view of the design.

27. Click on Floorplan and select Specify Floorplan.

49

Select the Aspect Ratio as per the requirement. Give some dimension in Core to left,
Core to right, Core to top,Core to bottom. e.g. give 30 to each. This is to create the
space for Power rings which will be created in power planning. Click OK and the Tool
window will be look like as below.

The core dimensions are changed.

28. Click on Floorplan and select Automatic Floorplan and select Plan Design. Click Ok.
This will automatically put the Macros if there are any in the design.
29. Next step is to do power planning. Click on power, select power planning and click
on Add Rings.

50

30. Select the top and bottom layer as Metal5, Left and Right as Metal6. Set the width as
per the requirement and taking the space between core boundary and I/O pad
considerations. Select the option for offset as center in channel and click OK.
The power ring will get created in between the channel. The image on the next page is
showing the power ring created.

51

31. The next step in power planning is to create power strips. Select Power, click Power
Planning and click Add Stripe.

52

32. For adding the stripes, select metal layer as Metal 6 and chose direction as vertical(if
direction chosen is horizontal, chose metal layer as Metal 5). Click OK and the design
will get the vertical thin strips of type Metal 6.

53

33. After the power planning, go to Route and click Special Route. A new Window
Sroute will appear.

54

34. Click OK with all default settings. This is done to provide power to standard cells.
The horizontal blue coloured metal1 stripes created as a result of Special Route.

35. For placement, click on place and select place and click on Place Standard Cell.

55

36. Click OK on Place window and in physical view the blue coloured standard cells can
be seen as a result of placement of standard cells.

56

37. Before CTS, timing analysis has to be done for any setup violations. Click on Timing,
and select Report Timing. A Timing analysis window will get open. In the window
select the Pre-CTS as Design Stage and select the Setup as Analysis Type.

57

58

38. Click OK to complet the Timing analysis. The timing information will get display on
terminal in tabular form. In the table displayed on the terminal under timeDesign
Summary, check for any negative value under WNS(Worst Negative Slack) and
TNS(Total Negative Slack). The terminal will look as the image below and Tool
window as on next page.

59

The multi-coloured lines visible in the tool window are the connections between standard
cells using metal layers. If any part of this design is Zoom-in, metal layers can be viewed
easily.

60

Different colours show different metal

39. If there is any of the negative slack value under WNS or TNS, click Optimize in Tool
window and Select Optimize Design. A new window Optimization will get open.
Select Pre-CTS as Design Stage and Setup as optimization type and click OK.
The tool will optimize the design and the optimized timing results will be displayed
over terminal again.

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In this case we did not get any negative slack, so this step is skipped here.
40. Go to Clock, click Synthesize Clock Tree, a new window Synthesize Clock Tree
will get open.

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41. Click on Gen Spec and a new window Generate Clock Spec will open.

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42. From Cells List, Select all clocks starting with CLK and click on Add button to add
them to the Selected Cells. Select a name for Output specification.

43. Click OK. Then specify a name for Results Directory. and click OK. The tool
window looks like the image below.

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44. Again Perform the Timing by clicking on Timing and selecting Report Timing. Select
Post-CTS under Design Stage and do the select Set-up as Analysis Type.

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45. Click Ok to perform the timing. The timing information will be displayed over the
terminal window. Again check for any negative slacks under WNS or TNS.

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46. If there is any negative value found for either of WNS or TNS then perform the
Optimization Technique to reduce the negative slack. No negative slack is found in
the terminal image on previous page so this step is skipped here.
47. Timing Analysis for Setup as Analysis Type is done. Repeat Step 27 for performing
timing for Post CTS as Design Stage and Hold as Analysis Type. The tool will
show the timing results in the terminal window.

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48. After Timing Analysis is performed, the timeDesign Summary is showing the
negative slack values for both TNS and WNS. Perform the Optimization. Go to
Optimize and click on Optimize Design. Select Post-CTS as and HOLD as the
Optimization Type

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49. Click OK to perform the Optimization and Tool will perform the optimization and
displays the optimized results in the terminal window under timeDesign Summary.
The results of Optimization can be seen on the next page in tabular form for both
Setup and Hold mode. As compare to the Timng Results performed for Hold mode in
Step 30, the design has been optimized and tabular results shows that all slack values
are now positive values and no more negative values for slack.

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50. Perform Routing by clicking Route, and select NanoRoute and then click Route. A
window NaoRoute will open.

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51. Click Ok to Perform Routing. The tool will Perform the Routing and the Routing
statistics can be seen on terminal window including DRC violations.

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52. After routing tool window looks like the below image.

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53. Perform the timing again. Go to Timing, seelct Report Timing and a Timing Analysis
window will get open. Select Post-Route as the Design Stage and Setup as
Analysis Type. Click Ok. The timing results will be displayed in terminal window for
Set up mode.

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Since there is no negative value of slack so design does not require optimization for Setup mode in Post-Route stage.

54. Repeat Step 36 for Post-Route as Design Stage and Hold as the Analysis Type.
Click OK. The timing results can be seen in the terminal window for hold mode.

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As there is no negative value of slack, the optimization is not require to perform. The
final view of the circuit is as below:

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