VLSI Design Circuits
VLSI Design Circuits
VLSI Design Circuits
Age of electronics
microcontrollers, DSPs, and
other VLSI chips are
everywhere
(Uyemura textbook)
Digital Camera
PDAs
MP3/CD Player
Laptop
Camcorder
Cell phone
Nintendo
Gameboy
Figure 1.2
(p.4)
General
overview of
the design
heirarchy.
Top
Down
Design
System Specifications
other technologies
passive circuits
III-V devices
Silicon BJT
Functional Simulation
Logic Synthesis
Digital Cell
Library
Post-Layout
Simulation
digital mainly
coded design
ECE 411
Chip Floorplanning
Chip-level Integration
Mixed-signal
Analog Blocks
Parasitic Extraction
Manufacturing
LVS
(layout vs. schematic)
Bottom Up Design
DRC
cell performance
Analog/mixed signal
ECE 410
Process
Design Rules
Process
Characterization
Process
Design
Physical Design
Simulation
VLSI Design
Procedure
Process Models
SPICE
Schematic Design
Bottom
Up
Design
Process Capabilities
and Requirements
Functional/Timing/
Performance Specifications
transistors /
chip
channel length
gate
source
drain
power /
transistor
Simplified Symbols
ECE 410, Prof. F. Salem
nMOS
pMOS
Lecture Notes Page 2.7
supply voltage
ref: Kuo and Lou, Low-Voltage CMOS VLSI Circuits, Fig. 1.3, p. 3
Moores Law
(ref: http://www.intel.com/intel/museum/25anniv/hof/moore.htm)
1.8 V
1.5 V
1.2 V
0.9 V
0.6 V
Year
1999 2001
Feature Size (nm) 180 130
0.6 V
2004
2008
2011
2014
90
60
40
30
* http://public.itrs.net/Files/2000UpdateFinal/ORTC2000final.pdf
Top
Down
Design
What is a MOSFET?
Digital integrated circuits rely on transistor switches
System Specifications
Definitions
Functional Simulation
Logic Synthesis
Digital Cell
Library
Post-Layout
Simulation
digital mainly
coded design
ECE 411
Chip Floorplanning
DRC
Simulation
Functional/Timing/
Performance Specifications
insulator
channel
------------
drain
silicon substrate
Process
Characterization
Process
Design Rules
Process
Design
Process Models
SPICE
Schematic Design
Bottom
Up
Design
gate
source
conductor
Physical Design
VLSI Design
Procedure
Oxide
Manufacturing
LVS
Poly
Mixed-signal
Analog Blocks
cell performance
Analog/mixed signal
ECE 410
Chip-level Integration
Parasitic Extraction
Bottom Up Design
Process Capabilities
and Requirements
Primary Features
Q+
fundamental equation
V
gate
insulator
- - drain
- -silicon substrate
Capacitance
fundamental equations
capacitor charge: Q = CV
capacitance: C = A/d
Topview
nMOS
source
gate
source
drain
nMOS
pMOS
VDD
VDD
+
-
CMOS
logic
circuit
CMOS
logic
circuit
V
VDD
Vin
pMOS
pMOS
drain
switching behavior
gate
drain
logic 1
voltages
undefined
logic 0
voltages
Lecture Notes Page 2.15
gate
Vout
+
Vgs
-
pMOS
Vin Vout (drain)
1
?
device is OFF
0
Vs=VDD=1 device is ON
pMOS
off
on
on
pMOS
nMOS
Vin Vout (drain)
1
Vs=0 device is ON
0
?
device is OFF
Vin
VDD
VDD-|Vtp|
source
switching behavior
Digital Behavior
nMOS
nMOS
Vgs > Vtn = on
+
Vsg
Vin
Vtn
source
pMOS
Vsg > |Vtp| = on
Vsg = VDD - Vin
gate
drain
off
nMOS
Vout
Rule to Remember
source is at
lowest potential for nMOS
highest potential for pMOS
nMOS
nMOS passes a good low (0) but not a good high (1)
pMOS passes a good high (1) but not a good low (0)
Vg
VDD
VDD
nMOS
on when gate
is high
VDD
0V
0V
pMOS
VDD
0V
Vy = VDD
Vsg=|Vtp|
+
Vg=5V, Vi=2V Vo = 2V
Vg=2V, Vi=2V Vo = 1.5V
Example (Vtn=0.5V):
Vy = |Vtp|
Vg
Vo
Vg=2V, Vi=5V Vo = 5V
Vg=2V, Vi=2V Vo = 2.5V
Example (Vtp=-0.5V):
y=?
y = x A, i.e. y = x if A = 0
y=x
For pMOS,
min(Vo) = Vg+|Vtp|
y = x A, i.e. y = x iff A = 1
=?
For nMOS,
max(Vo) = Vg-Vtn
pMOS
Rule to Remember
source is at lowest potential (nMOS) and highest potential (pMOS)
Vi
Vy =
VDD-Vtn
Vy = 0 V
0V
on when gate
is low
+
Vgs=Vtn
-
a+b=ab
inputs
assert-low pMOS
logic
output
assert-high
nMOS
logic
nMOS
assert-low pMOS
logic
output
inputs
assert-high
nMOS
logic
+
Vsg
Vin
source
gate
pMOS
Vsg > |Vtp| = on
Vsg = VDD - Vin
Vg=
Vin Vout
0 1 on = closed
1 ? off = open
nMOS
Vgs > Vtn = on
Vg=
Vin Vout
0 ? off = open
1 0 on = closed
drain
drain
Vin
gate
+
Vgs
-
source
pMOS
nMOS
+
Vgs=Vtn
-
VDD
VDD
0V
Vy =
VDD-Vtn
Vy = 0 V
0V
nMOS
pMOS
VDD
assert-high switch
off
0 in = 0 out
VDD in = VDD-Vtn out
strong 0, weak 1
pMOS
VDD in = VDD out
0 in = |Vtp| out
strong 1, weak 0
Vy = |Vtp|
series = AND
parallel = OR
assert-low switch
=x
y = x A, i.e. y = x if A = 0
series = NOR
on
Vtn
All standard Boolean logic functions (INV, NAND, OR, etc.) can be
produced in CMOS push-pull circuits.
y = x A, i.e. y = x iff A = 1
off
on
nMOS
0V
Vsg=|Vtp|
+
Vy = VDD
VSS = ground
ECE 410, Prof. F. Salem
0V
pMOS
nMOS
Vin
VDD
VDD-|Vtp|
assert-high
nMOS
logic
Logic Properties
DeMorgans Rules
(a b) = a + b
(a + b) = a b
parallel = NAND
ECE 410, Prof. F. Salem
assert-low pMOS
logic
output
CMOS Inverter
Inverter Function
Inverter Symbol
0
1
Vin=VDD
y =x
1
0
nMOS Inverter
(b) nMOS is on
output is low (0)
+
Vsg
-
nMOS NOR
nMOS NAND
pMOS
Vin
Vout = Vin
c = ab
c = a+b
nMOS on
output low (0)
+
Vgs
-
nMOS
x
x+y
Karnaugh map
0
0
1
1
0
1
0
1
x+y
y 0
g(x,y) = x y 1 + x 0 + y 0
1
0
0
0
y
g(x,y) = x + y
g(x,y) = x y 1 + x 0 + y 0
Important Points
series-parallel arrangement
when nMOS in series, pMOS in parallel, and visa versa
true for all CMOS logic gates
allows us to construct more complex logic functions
ECE 410, Prof. F. Salem
NAND Symbol
x y
xy
x
0
0
1
1
xy
CMOS Schematic
0
1
0
1
3-Input Gates
K-map
y 0
1
1
1
0
what function?
x+y+z
x
y
z
y
z
g(x,y) = x+y+z
NAND3
Alternate Schematic
NOR3
= x. y.0 + x .1 + y .1
g(x,y) = x y
y
x
y
z
xyz
NAND Schematic
y
x
g(x,y) = x y z
z
f = a (b + c),
y
g(x,y) = x y
g(x,y) = x + y
y
x
f = (d e) + a (b + c)
a+b=ab
Using DeMorgan
DeMorgan Relations
NAND-OR rule
ab=a+b
F = f(a, b, c)
x y
g(x,y) = x + y = x y
x+y
Series-connected pMOS
NOR-AND rule
a+b=ab
equivalent
to
x y
x y
x+y
g(x,y) = x y = x + y
assert-low AND
creates NOR function
pMOS
nMOS
6 transistors
(CMOS)
Fn = a (b + c)
Apply DeMorgan
none needed
Resulting Schematic
Resulting Schematic
F=a(b+c)
a
F=a(b+c)
b
c
Fn = f(a, b, c) = F
EXAMPLE:
g(x,y) = x y
F = ab
y
x
Fp = a b = a+b;
OR/parallel
Fn = ab = ab;
AND/series
ECE 410, Prof. F. Salem
Structured Logic
Recall CMOS is inherently Inverting logic
Can use structured circuits to implement general logic
functions
AOI: implements logic function in the order
AND, OR, NOT (Invert)
Example: F = a b + c d
operation order: i) a AND b, c AND d, ii) (ab) OR (cd), iii) NOT
a
b
Fp = f(a, b, c)
assert-low OR
creates NAND function
bubbles = inversions
x+y
x
y
x
equivalent
to
F=a(b+c)
F=ab+cd
(series/parallel)
(series/parallel)
F = (a +e) (b +f)
Complete CMOS
AOI/OAI circuits
eX
bX
error in textbook Figure 2.45
ECE 410, Prof. F. Salem
nMOS
3 operations:
1 AND, 2 OR
# txs =
pMOS
Group 2: c & d in series
Group 1: b parallel to G1
Group 3: a in series with G2
10
pMOS
Apply DeMorgan expansions
Invert inputs for pMOS
Fp = a (b + c)
Resulting Schematic ?
F = a b (a + c)
nMOS
nMOS
none needed
Apply DeMorgan
Fn = a + (b+c )
Fn = a + (b c)
Resulting Schematic ?
Invert Output
c
Fn = a b (a + c) = a b + (a + c)
F=a b (a+c)
Fn = a b + ( a c)
Reduce Function
Fn = a (b + c)
Resulting Schematic ?
Complement operations for pMOS
Fp = a + (b c)
Exclusive-OR (XOR)
ab=ab+ab
not AOI form
a
b
Exclusive-NOR
ab=ab+ab
inverse of XOR
XOR: a b = a b + a b
XNOR: a b = a b + a b
ECE 410, Prof. F. Salem
11
schematic
symbol
y = x s, for s=1
More TG Functions
TG XOR and XNOR Gates
ab=ab+ab
= a b, b = 1
ab=ab+ab
= a b, b = 1
= a b, b = 1
= a b, b = 1
= a, a = 1
f=a+ab
= a b, a = 1
f=a+b
12