Analog FFT Interface for Ultra-Low Power

Analog Receiver Architectures

Nima Sadeghi
Hessam M. Nik

Christian Schlegel
Vincent C. Gaudet

iCORE High Capacity Digital Communication Lab

Department of Electrical & Computer Engineering
University of Alberta
Edmonton, Alberta Canada T6G 2V4
(nima, hessam, schlegel, vgaudet)@ece.ualberta.ca

System Model

Abstract Our project is to design and implement an analog

receiver including an analog decoder and a low power analog
FFT processor. The FFT can be represented by a graph that is
similar to the underlying graph in iterative decoders, and could
!
potentially be implemented using comparable analog circuits with
simple structures. Our system uses an OFDM with differential
BPSK modulation. We simulated the system, modeled the transistors mismatch and simplified the circuit for the 256-bit FFT.
Our goal is eventually to design the FFT processor in CMOS
0.18m technology in low power subthreshold regime.

I. I NTRODUCTION

MN coded bits

{-1, +1}

"

"

Encoder

At the system level we look at a communication system

model which consists of a transmitter, communication channel,
and receiver as shown in Fig.1. We explain each individual part
in this model now and at the end we look at the bit error rate
performance results.
At the transmitter binary information bits are encoded by
an error correcting code such as a Turbo or LDPC code
in our case. A serial-to-parallel data converter gives M*N
coded bits to a symbol mapping block to generate N 2M ary
symbols. We will concentrate on BPSK, i.e., M=1. The
mapping is differential to avoid phase recovery. The Inverse

Serial
To
Parallel
!

.
.
.

MN

Offset
frequency AWGN

N M-arry symbols

Symbol
Mapping
Circular
!
Differential
Modulator

.
.
.

Sb ( t )

RF

I/Q

Upconversion

IFFT

!
MN estimated bits

b
"

j 2 "#f1

Complex
Multiplier

.
.
.

MN

I/Q

!e
!
FFT

j 2 "#f n

sn

!
Receiver

n(t)

Channel

Timing information available

s1

.
.
.

j 2 "#f (t )

SRF(t)
!

N noisy M-arry symbols

r
Decoder

!
N

Transmitter

II. S YSTEM OVERVIEW

For ultra-low power applications High Capacity Digital

Communication Lab has designed an analog receiver consisting of a (256,121) Turbo Product Decoder [1] and we
want to build an FFT interface to extend this project. We
propose to use the OFDM transmission format due to its
versatility and process simplicity [2]. This requires that the
receiver transforms received sampled signals by a Fast Fourier
Transform (FFT) to generate the LLR values required by the
analog decoder.
A 256-bit FFT designed and simulated in Matlab. In our
simulations we considered the transistors mismatch due to
the process variations and some circuit simplifications to
implement it eventually using CMOS technology. Our figure of
merit to design such a low-power analog FFT is not to degrade
the decoder performance defined by its SNR. In this work
first we look at the system level design and its mathematical
representation. Then we explain the FFT structure and some
circuit considerations. At the end we discuss the system
performance and the simulation results.

S1
. Serial
To
.
. Parallel
!
I/Q
Sn

(n"Ts )
Ts=

T
N

RF
DownI/Q conversion

Channel model at the receiver

!

Fig. 1.

OFDM communication system model.

Fast Fourier Transform (IFFT) creates an orthogonal frequency

division multiplexed (OFDM) transmission signal. The IFFT
creates both in-phase and quadrature channels. After RF
up-conversion, the complex equivalent baseband signal S(t)
with a symbol period [0,T], containing SI (t) and SQ (t), is
transmitted.
At the receiver, the RF signal is down-converted. The signal
is sampled at times nTs producing S(nTs ) = Sn where
T
Ts = N
. We assume that the timing information is available
at this point. After sampling, we can model the channel at the
receiver. We add additive white Gaussian noise (AWGN), and
consider frequency offsets, ej2fk , multiplying each sample.
The n noisy samples are demodulated by an N point FFT
processor. For symbol detection, we use a circular differential
demodulator in which we multiply adjacent samples to cancel
out the unknown common phase offset. The estimated samples
are delivered to the error control decoder to recover the
original transmitted bits.

A. Mathematical View of the System

1) OFDM Transmitter: The data symbols dn for the different frequency channels are in general complex, i.e., dn = an +
jbn . Using the IFFT generates the I/Q baseband waveform
Sb (t) = SI (t) + jSQ (t) where

N
1
X

Sb (t) =

By reordering the sums in (9) we obtain

!
dk ejk t

0tT

(1)
yk = dbk =

k=0

N 1
N 1
1 X X j2n(lk)
dl
e N
N
n=0

(10)

l=0

N1
X

SI (t) = Re

!
dk e

jk t

(2)

k=0

N
1
X

0tT

k=0
N1
X

!
dk e

jk t

(3)

k=0

N
1
X

(ak sin(k t) + bk cos(k t)) ;

0tT

In (1) k = 2fk , where fk = kf , f = T1 is frequency

spacing to generate the different baseband frequency channels.
After generating baseband OFDM signals, we up convert it
by the RF carrier frequency fc ,


SRF (t) = Re Sb (t)ejc t
= (SI (t) cos(c t) SQ (t) sin(c t)) ;

(4)
0tT

In (4) c = 2fc . We transmit

SRF (t) = Re Sb (t)ejc t rect(t/T)

(5)

where rect(t/T) is 1 if 0 t T and zero elsewhere. To

discuss the receiver architecture and the recovery technique
we look at the baseband received OFDM signals after downconversion in which fc is removed. We consider it as a
complex envelope signal, received Sb (t).
2) Receiver Architecture: At the receiver we sample the
T
signal Sb (t) at tn = nTs , where Ts = N
to create the discrete
samples for the FFT given by:
N
1
X

dk ej2kf nTs , 0 n N 1

(6)

k=0

We rewrite (6) by substituting dn = an + jbn , f =

T
Ts = N
Sn =

N
1
X

(ak + jbk )e

j2kn
N

,0 n N 1

1
T

1
N

Sn e

j2kn
N

(7)

(8)

n=0

Substituting Sn from (7) we obtain

N 1 N 1
j2n(lk)
1 X X
yk = dbk =
dl e N
N n=0
l=0

dk e

j2kn
N

ej ;

0nN 1

(12)

k=0

which is a rotation of the original data, ak and bk , by . Here

we assume that the phase offset is constant for all n samples.
If it is not known we may use differential modulation.
Consider the following differential QPSK modulation as
example, in which the data are modulated differentially as
3

, ,
(13)
2
2
where k1 is a phase reference for symbol dk , and k
is our original coded information bit, ck . If we conjugate each
coming complex symbol at the receiver and multiply it by the
next symbol, we obtain the original data regardless the phase
offset.
dk = ejk = ej(k1 +k ) ;

k = 0,

rk = (yk1
)(yk ) = (dk1 )ej dk ej
j(k1 ) j(k1 +k )

=e

j(k )

=e

(14)
= ck

To generate the phase reference for the first symbol c1

for differential modulation we use a tail-biting method; we
consider dN from the previous block is the same as d0 for the
new block. At circular differential modulator we add the phase
of the adjacent coded information bits ck , using multiplication
dk = ck dk1 ;
1kN
d0,Current = dN,P revious

We can recover our transmitted data using the FFT as

follows:
yk = dbk =

N
1
X

and

k=0

N
1
X

Thus far we have assumed that the channel is ideal and we

showed that data recovery can be accomplished via an FFT
transformation.
3) Phase Offset Consideration: Now consider the receiver
samples when there is a phase offset . The new samples Sn
are now given from (7) by
Sn =

k=0

Sn =

(11)

l=0

(ak cos(k t) bk sin(k t)) ;

SQ (t) = Im

N 1
1 X
yk = dbk =
dl N (l k) = dk
N

(9)

(15)

and at the demodulator we subtract the phase of the adjacent

noisy symbols yk , using complex multiplication

yk1
yk = ck ;

1kN

(16)

After differential demodulation, N estimated symbols are

delivered to the decoder to extract information bits as depicted
in Fig.1.
The phase offset is taken care of by using this differential
scheme at the cost of N=256 number of complex multipliers
at the receiver front end between the FFT processor and the
decoder.

8-bit
Diagram:
III. FFT
256- BITButterfly
FFT I MPLEMENTATION
x[0]

128

256

128

X[0]

64
64

-1

x[1]
x[2]

-1

-1

X[6]

W82
x[4]
x[5]

X[1]

-1
-1

-1

W8
x[6]

-1

x[7]

-1

X[5]

W82

X[3]

-1
-1

W83

32

-1

X[7]

W82

Fig. 2. Butterfly Diagram of an 8-bit FFT. The inputs and outputs

are complex differential values and W8 1 , W8 2 and W8 3 are complex
absolute values.

The butterfly diagram of an 8-bit FFT processor is depicted

in Fig. 2 [3]. Looking at this diagram we observe that additions
and multiplications by constant complex values, W 1 , W 2 and
W 3 , are the only two operations required to create an FFT
processor. It is well suited for implementation using analog
CMOS circuits based on the fact that adding the currents is
just tying two wires together and weighting can be achieved
by transistor sizing. Therefore the FFT block can be simply
implemented in CMOS technology by using current mirrors
as basic blocks.
Each input in the butterfly graph is a complex differential
value
xk = (xki+ xki ) + j(xkq+ xkq )
(17)

WN

WN

2k
2k
+ j sin
= W Fi + jW Fq (18)
N
N
where N is the number of points in the FFT and the W Fi
and the W Fq are Weighting Factors,WFs, to operate with the
real and imaginary parts of its input signals respectively.
In Fig. 3 we have extended the 8-bit FFT diagram to obtain
the 256-bit FFT structure. One can see that the sub-block 4
FFT and 8 FFT in this graph are exactly the same as those
depicted in Fig. 2. It is straightforward to follow the algorithm
shown in Fig. 3 to generate any larger FFT.
j2k
N

= cos

A. Circuit consideration
As mentioned above, the entire 256 FFT processor can be
built in CMOS technology using only current mirrors. On
Fig. 2 all white dots are current mirrors without scaling,
i.e. having the same W/L ratio. The dark crossed circles
are complex multipliers which contain 4 current mirrors with
different scaling factors to generate complex multiplication of
17 and 18. The black dots are summation nodes realized by
tying wires together.

WN

WN 0

WN

WN 4

WN

WN 8

.
.
.

WN 8
WN16
.
.
.

WN

WN124

WN126

WN127

WN 0

.
.
.

.
.
.

WN 2

16

WN 0

120

WN16

WN 0

WN32

WN32

.
.
.

WN64

WN112

4
4

2
2

WN0
WN64

WN96

N=256

(WN)1 (WN)2 (WN)4 (WN)8 (WN)16 (WN)32 (WN)64 W 0=1

N
256-bit FFT: Weighting Factors on Butterfly Diagram.

Fig. 3.

The weighting factors on the last stage of the 256 FFT

shown in Fig. 3 contain all other WFs in all other lower stages.
Therefore the number of different weighting factors is 128.
Due to the circular distribution of WFs on the unity circle and
our complex differential signals model, we actually do not
need to generate all different values of the 256FFT diagram.
We can interchange the real-imaginary and/or positive-negative
signals properly to reduce the number of different values for
WFs by a factor of four, i.e., 32 different values for all WFs
existing on 256 FFT. This idea has been illustrated graphically
in Fig. 4.
wN64
q

and the Ws are complex values on the unity circle

WN k = e

16

X[2]

-1

x[3]

32

X[4]

2.

i- <--> i+
i <--> q

3.
i- <--> i+

128 1.
64
i <--> q
32
16
Available

120

wN128

w
126 wN124 N
wN127 wN

iw 0
N

wN112 wN96 wN64 1 2

Rings Order:

Inner to outer

5
9
17
Available WFs

33

2 --> 128

quadrature
in-phase

Fig. 4. The circular view of the Weighting Factors on the unity circle.

The basic current mirror circuit [4] is shown in Fig. 5. To

use this circuit just for mirroring the scaling factor, WF, should
be 1. We modeled the mismatch between transistors in each
current mirror as an additive white Gaussian random variable

Multiplier / Scaling factor:

in-phase
or
quadrature
and we checked how sensitive the FFT is to the different values
of the variance of this random variable as a model for common
non-ideal technology variations. We explain its impact in the
simulation result section.

!1

10

" :Mismatch Model; Gaussian Noise

in

out

256!bit FFT Performance

10

= WF"I in (1+ #)
!2

(W L)

(W L)

( )

= WF " W L

Bit Error Rate

10

!3

10

Current mirror: basic circuit to implement FFT. is a white

Gaussian random variable to model the transistors mismatch.
Fig. 5.

!4

10

Simulation Differential BPSK Demodulation Ideal FFT, Mismatch Tolerance:0

Simulation Differential BPSK Demodulation Real Model FFT, Mismatch Tolerance:0.05
Simulation Differential BPSK Demodulation Real Model FFT, Mismatch Tolerance:0, Simple circuit
Simulation Differential BPSK Demodulation Real Model FFT, Mismatch Tolerance:0.05, Simple circuit

IV. S YSTEM P ERFORMANCE AND S IMULATIONS

A. System Performance
Considering the BER vs. SNR performance, for large constelations the power of noise is doubled when using differentially coherent detection versus a coherent technique. The
power performance of differential QPSK compared to common
coherent PSK is about 2.3 dB worse at BER of 104 ; however
for differential BPSK it is less than 1 dB [5].
In a spread spectrum scenario the limiting factor is interference from different users. Therefore by using higher order
modulation designers try to get higher spectral efficiency, i.e.,
the differential QPSK in general is more spectrally efficient
than differential BPSK. However in spread spectrum communication with multiuser channel the spectral efficiency of an
N-QPSK system is the same as a 2N-BPSK.
The advantage of using differential BPSK in this standard
is to gain more power efficiency, as explained above, while
the spectral efficiency remains the same by doubling the users
compared to differential QPSK modulation. Therefore we have
chosen differential BPSK modulation for our system.
B. Simulation results
We simulated the system shown in Fig. 1 first without an
encoder/decoder. We used an ideal 256-FFT to get the exact
performance of uncoded differential BPSK transmission. We
measured the sensitivity of the 256-FFT both to the transistor
mismatch and values of weighting factors.
Fig. 6 shows the bit error rate, (BER), performance curve
Eb
of the system versus signal to noise ratio, SN R = N
. On
0
this plot the star-dot solid line is the ideal 256-FFT. The
circle-dot solid line represents the results for considering 5 %
tolerance, i.e. the variance of the random variable is (0.05)2 ,
on every current mirror node in the entire 256-FFT processor.
The performance loss due to this mismatch is about 2 dB at
BER 103 .
Also in another simulation we used only 3 different values
of weighting factor rather than 32, shown in Fig. 4, to simplify
the circuit. The results are dashed lines on the plot. The loss
is less than 1 dB. Consequently the FFT is more sensitive

Theory Dif.BPSK w/o decoder Ideal FFT

!5

10

5
6
SNR = Eb/N0 (dB)

Fig. 6. Simulation results for ideal, mismatch modeled, and simplified

256FFT.

to mismatch between the transistors than the exact value of

different weighting factors.
As a next step we are now simulating the entire system
including encoder/decoder. The decoder decreased the loss of
2 dB at BER 103 due to mismatch by more than 1 dB.
Based on the system simulation we have plan to design a
256-FFT circuit operating on subthreshold regime in CMOS
0.18m technology using Cadence and eventually fabricate it
by the support of the Canadian Microelectronics Corporation.
V. C ONCLUSION
The fundamental goal of our project is to move towards
system-level integration of analog decoders with other basic
communications receiver components, while maintaining the
power consumption advantages of analog decoders to make
them suitable for use with energy scavenging methods. We
modeled the actual 256-FFT circuit, considering mismatch
and circuit simplification of weighting factors on our communication system to find the performance of the system.
The decoder decreased the performance loss due to the circuit
mismatch. Therefore the analog 256-FFT could be used as an
input interface for our analog decoder to satisfy the low power
consumption constraint.
R EFERENCES
[1] C. Winstead, Analog Iterative Error Control Decoders, Doctor of
Philosophy thesis, Dept. of Elec. & Comp. Eng., University of Alberta,
2004.
[2] J.G. Proakis, Wiley Encyclopedia of Telecommunications.,Vol. 4, John
Wiley & sons Inc., New Jersey, 2003.
[3] A. V. Oppenheim, R. W. Schafer and J. R. Buck Discrete-time signal
processing, 2nd ed., Prentice-Hall Inc., New Jersey, 1999.
[4] S. Liu, Kramer, Indiveri, Delbruck, and Douglas. Analog vlsi: Circuits
and principles., The MIT Press, Cambridge, Massachusetts, 2002.
[5] J.G. Proakis, Digital Communications, 4th ed., McGraw-Hill, New York,
NY, 2001.

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