Chapter 10

Logic Built-in Self test

2
Outline
Introduction
Test Pattern Generation
Response Analyzers
BIST Examples
3
Definition & Advantages of
BIST
Built-In Self-Test (BIST) is a design-for-
testability (DFT) technique in which testing
(test generation , test application) is
accomplished through built-in hardware
features.
[ V.D. Agrawal, C.R. Kime, and K.K. Saluja ]
Can lead to significant test complexity
reduction
Especially attractive for embedded cores
4
Benefits of BIST
Complexity
Testing is a global problem.
Partitioning, which reduces design complexity, does not
reduce the testing complexity.
Or worse, Connection of blocks usually introduces
redundancy and reduces fault coverage.
With BIST, tests can be applied systematically
Component test; Interconnect test; PCB test; System test
A
B
Test set
for A
Test set
for B
A
B
C
Test set
for C?
Designer 1
Designer 2
?
5
Quality
For some large systems (Motorola six sigma project),
keeping the defect level to 10 ppm or better is only
possible through BIST.
Test generation
Its difficult to deliver patterns through layers of design
hierarchy.
Local test pattern generation (BIST) reduces the test
generation and delivery efforts.
Test application
BIST allows electronic rather than physical probes,
and thus reduces test application cost.
Test development time
BIST circuitry should be automatically generated by
CAD tools.
6
BIST Associated Costs
Area overhead
Additional gate counts and routing resources
Pin overhead
Usually 1 pin at least is needed to invoke the BIST operation.
Integrate with 1149.1 is desirable
Performance overhead
Due to delays added to signal paths
Yield loss and reliability reduction
Due to increase die size
Increased design effort and time
Shift test efforts into design domains
Testability of the BIST hardware
Self-testability of added hardware
7
BIST Costs Distributed Among
Components
Extra design time is compensated by reduced test
development cost.
Can the benefits in other factors balance the increased
fabrication cost?
To evaluate test strategies under economic models
Design &
test
Fabrication
Production
test
Maintenance test
Diagnosis & repair
Service interruption
Chips
+/- + -
Boards
+/- + - -
Systems
+/- + - -
8
Reality of Logic BIST
BIST is NOT a replacement for scan
it can be built on top of full-scan
BIST does NOT result in fewer patterns
it usually uses many more patterns than ATPG patterns
BIST does NOT remove the need for testers
tester still required to
initiate test
read response
apply ATPG patterns to other part of IC
With proper designed BIST, the added cost will be more than
balanced by the benefits in terms of reliability and reduced
maintenance cost
9
General Organization of BIST
Test Generator
Circuit Under Test
(CUT)
Response Compressor
To avoid expensive
bit-to-bit comparison
Simple on-chip
pattern generation
+
signature
off-line
pre-computed
fault-free
signature
Pass-or-fail
10
Outline
Basics
Test Pattern Generation
How to generate patterns on chip using minimum
hardware, while achieving high fault coverage
Response Analyzers
BIST Examples
11
On-Chip Pattern Generation
Hardware Types
Stored Patterns
Counter Based
LFSR Based
Cellular Automata
Pattern Generated
Deterministic
Pseudo-Exhaustive
Pseudo-Random
12
Pseudo-Random Pattern
Generation
Pseudo-Random
Patterns generated in a pre-determined order
but appeared to be random (low correlation
between adjacent bits).
Implemented by Linear Feedback Shift
Register (LFSR) or Cellular Automata (CA)
Most popular BIST circuits
Easy implementation
Low hardware costs
13
Linear Feedback Shift Register
(LFSR)
Linear: superposition principle applicable
Response to linear combination of stimuli is the linear combination of
the responses to the individual simuli.
Simple and regular structure
No input except clocks is supplied: autonomous machine
Components:
Shift registers: one cycle delay implemented by flip-flops
XOR gate: modulo-2 addition
D1 D2 D3 D4
+
D1 D2 D3 D4 +
Type 1: external-XOR LFSR Type 2: internal-XOR LFSR
z
y1 y2 y3
y4
y1 y2
y3
y4
z
z = y4 + y1 = D
4
(z) + D(z)
z = y4 = D(y3 + y4) = D(D
3
(z) + z)
= D
4
(z) + D(z)
Type 1: external-XOR LFSR
14
X
0
(t + 1)
X
1
(t + 1)
.
.
.
.
X
n-3
(t + 1)
X
n-2
(t + 1)
X
n-1
(t + 1)
1
0
.
.
.
.
0
0
h
1
0
1
.
.
.
.
0
0
h
2
0
0
.
.
.
.
0
0
1

0
0
.
.
.
.
1
0
h
n-2
0
0
.
.
.
.
0
1
h
n-1
X
0
(t)
X
1
(t)
.
.
.
.
X
n-3
(t)
X
n-2
(t)
X
n-1
(t)
=
X (t + 1) = T
s
X (t)
characteristic function: f (x) = 1 + h
1
x + h
2
x
2
+ + h
n-1
x
n-1
+ x
n
T
s
Type 2: internal-XOR LFSR
15
X
0
(t + 1)
X
1
(t + 1)
X
2
(t + 1)
.
.
.
X
n-3
(t + 1)
X
n-2
(t + 1)
X
n-1
(t + 1)
0
0
1
.
.
.
0
0
0
0
0
0
.
.
.
0
1
0
0
1
0
.
.
.
0
0
0

0
0
0
.
.
.
0
0
1
X
0
(t)
X
1
(t)
X
2
(t)
.
.
.
X
n-3
(t)
X
n-2
(t)
X
n-1
(t)
=
0
0
0
.
.
.
0
0
0
X (t + 1) = T
m
X (t)
characteristic function: f (x) = 1 + h
1
x + h
2
x
2
+ + h
n-1
x
n-1
+ x
n
1
h
1
h
2
.
.
.
h
n-3
h
n-2
h
n-1
T
m
16
LFSR State Diagram
0000
The register cycles through 2
4
-1 states
if the seed is not all-0
1000
0001
1100
0010
1110
1111
0111
1011
0101
1010
1101
0100
1001
0011
0110
17
LFSR Example
0 0 0 1
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1
1 0 1 1
0 1 0 1
1 0 1 0
1 1 0 1
0 1 1 0
0 0 1 1
1 0 0 1
0 1 0 0
0 0 1 0
0 0 0 1
1 ) (
3 4
+ + = x x x g
repeating
Characteristic polynomial
D0 D1 D2 D3
+
z y3 y2 y1 y0
y0(t+1)
y1(t+1)
y2(t+1)
y3(t+1)
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 1
y0(t)
y1(t)
y2(t)
y3(t)

0 3 3
D D D + =
2
D
1
D
0
D
18
LFSR Characteristics
Maximum-length sequence
A sequence generated by an n-stage LFSR is called a
maximum-length sequence if it has a period of 2
n
-1
A LFSR can generate maximum-length sequence if its
characteristic polynomial is primitive.
Primitive polynomial
The characteristic polynomial associated with a
maximum-length sequence is called a primitive
polynomial
Primitive (irreducible) polynomials
cannot be factorized into two (or more) parts, i.e., it is
not divisible by any polynomial other than 1 and itself.
19
LFSR Properties As a Pattern
Generator
Pseudo-random sequence
The sequence generated by an LFSR is called a
pseudo-random sequence
No. of 1s and 0s
The number of 1s in a maximum-length sequence
differs from the number of 0s by one
Transition Count
The number of transitions between 1 and 0 that an
m-sequence makes in one period is (m+1)/2.
The correlation
Between any two output bits is very close to zero
20
When only a fraction of the 2
n
-1 can be applied,
LFSR is better than counters.
Counter LFSR
0 0 0 1 0 0
0 0 1 1 1 0
0 1 0 1 1 1
0 1 1 0 1 1
1 0 0 1 0 1
1 0 1
1 1 0 0 1 0
1 1 1 0 0 1
Sequences of LFSR is more random
Every bit is random
21
Autocorrelation between different bits:
The autocorrelation function of every maximum-
length LFSR of period p=2
m
-1 is:
C(0)=1
C()=-1/p i j

= =
= =

=
1 1
0 1
,
1 2
1
) (
1 2
1
n
a when
n
b
n
a when
n
b
where
n
b
n
b
m
C
m
n

D
1
D
2
D
3
k=3
1 0 0
1 1 0
1 1 1
0 1 1
1 0 1
0 1 0
0 0 1
Ex:
C(1,2)=-1/7
C(1,3)=-1/7
C(2,3)=-1/7
22
Cellular Automaton (CA)
An one-dimensional array of cells
Each cell contains a storage device and next
state logic
Next state is a function of current state of the
cell and its neighboring cells
D
Q
Next
State
D
Q
D
Q
Next
State
Next
State
Three-cell neighbor
. . .
. . .
23
Rule Number
Rule Number is the name of CA functions
Is determined by its truth table
State A0 A1 A2 A3 A4 A5 A6 A7
Ci+1
Ci
Ci-1
Next State K-Map FCA
A0 A1
A4 A5 A7
A3 A2
A6
Name A
i
i
i
=
=

0
7
2
Example:
F C C
CA i i
=
1
Rule = 64+32+4+2
= 102
0 1 0 1
(defined by Wolfram)
0 1 0 1
C
i
C
i-1
00 01 11 10 C
i+1
0
1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
24
Cellular Automata Hardware
CA with Null Boundary Condition
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
0
0
Standard All the CAs are of the same type
Hybrid The CAs are of different type
25
Cellular Automata Hardware
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
CA with cyclic Boundary Condition
26
Cellular Automata Example: Null-Boundary
Hybrid Using Rule 90 and 150
D
Q
90
D
Q
150
D
Q
90
D
Q
150
0
0
Rule 90: C
i
(t+1)=C
i-1
(t)C
i+1
(t)
Rule 150: C
i
(t+1)=C
i-1
(t) C
i
(t) C
i+1
(t)
The construction of pseudo-random pattern generator using CA has no
definite rule like searching for primitive polynomials.
D
4
D
2
D
1 D
3
27
Example of Last Pages Cellular
Automata: State Transitions
CAs have no shift-
induced bit value
correlation as LFSR.
A linear phase shifter
can make LFSR
patterns more
random
1 0 0 0
0 1 0 0
1 1 1 0
1 1 1 1
1 1 0 0
1 0 1 0
0 0 0 1
0 0 1 1
0 1 1 0
1 0 1 1
0 0 1 0
0 1 0 1
1 1 0 1
1 0 0 1
0 1 1 1
1 0 0 0
D
4
D
2
D
1
D
3
28
Fault coverage of Pseudo-Random
Patterns
Is a function of the test length and the
random testability of the circuits
Certain faults have very few patterns to
cover them
These faults have very low probability to be
detected by random patterns
Certain circuits are more resistant to
random patterns than others
If it has more such faults
29
Random Pattern Resistant
Faults
An RPRF cannot be detected by random patterns, which is a major
cause of low fault coverage in BIST
Inadequate coverage can be boosted by
Test point insertion
Stored ATPG patterns (reseeding)
Weighted random patterns
Fault coverage
Pseudo-random pattern length
Fault coverage loss
30
Example: Hard-To-Detect Fault
Hard-to-detect faults
Faults that are not covered by random testing
E.g., an output signal of an 18-input AND gate
Hard-to-detect fault
x
stuck-at-0
31
Weighted Pseudo Random
Testing
LFSR
1/8 3/4 1/2 7/8 1/2
0.8 0.6 0.8 0.4 0.5 0.3 0.3
0
D
Q
123
D
Q
193
D
Q
61
D
Q
114
D
Q
228
D
Q
92
D
Q
25
0
LFSR Based Weighted Cellular Automaton
It was observed that weighted random patterns could
achieve higher fault coverage in most cases !
32
Signal of An Arbitrary Weight
To implement a signal
with a signal-1 probability (weight) of 5/32
Procedure
(1) Decompose into a sum of basic weights
5/32 = 4/32 + 1/32 = 1/8 + 1/32
(2) Use AND and OR gates to realize the weight
L
F
S
R
a signal with a
weight of 5/32
1/8
1/32
z = y
1
y
2
y
3
+ y
1
y
2
y
3
y
4
y
5
y1
y2
y3
y4
y5
33
Control Register
State
Approximate Signal
Probability
1000 .5
0100 .25
0010 .125
0101 .75
0011 .875
1100 .625
1010 .5625
0110 .3437

Programmable Weighted PRPG

+
Central Register
4 3 2 1
1
2
3
2
5
7
15
10
16
Output
34
Optimal Weights to Inputs of
AND/OR Gates
Theorem: The optimal signal probability
assignment to the inputs of an AND or NAND
gate with n inputs is (n-1)/n.
Theorem: The optimal signal probability
assignment to the inputs of an OR or NOR
gate with n inputs is 1/n.
35
Heuristic for Signal Probability
Assignment
For each gate in the circuit do:
Begin
Step 1: Assign to the gate inputs the asymptotic optimal
assignment according to the theorems in last slide
Step 2: Moving backward from the lines being assigned
in Step 1, compute the signal probability assignment at
the primary inputs by propagating signal probability
values from outputs toward inputs according to the
formulas shown in the next slide
Step 3: Record the signal probability assignments
computed for the primary inputs
End
36
Step 4: To each primary input, assign a weight which
equals the average of all signal probability assignments
recorded in Step 3. Use this weight as the signal
probability of the primary input in a weighted random test.
Rules used in Step 2:
For primitive gates: (the input and output signal
probabilities are denoted as p
i
and p
0
):
A k-input AND gate: p
i
= (p
0
)
1/k
A k-input OR gate: p
i
= 1 - (1 - p
0
)
1/k
An INVERTER: p
i
= 1 - p
0
A k-input NAND gate: p
i
= (1 - p
0
)
1/k
A k-input NOR gate: p
i
= 1 - (p
0
)
1/k
For a fan-out with branch signal probabilities p
i
,
i = 1,2,k, the stem signal probability p
s
is

=
=
k
i
i s
p
k
p
1
1
37
G1 G4
G2
G3
.293
.206
.5
.5
.293
(a)
.63
X2
X3
X4
X5
X6
X1
.206
The computed weights for the primary inputs
An Example
Backtracing the local
requirement for gate G
4
G1 G4
G2
G3
(.5, .293)
(b)
X2
X3
X4
X5
X6
X1
(.333, .206)
(.666, .747, .63)
38
The nearly optimal signal probability assignment.
An Example (Contd)
G1 G4
G2
G3
.397
(c)
X2
X3
X4
X5
X6
X1
.27
.681
39
w1
w2
F2
F1
X
X will be assigned with (W
1
+W
2
)/2. However, W
1
and W
2
are two extreme values.
The Problem With the Heuristic
Multiple weights needed for 100% coverage.
Costs similar to stored selected patterns
40
On-Chip Exhaustive Testing
Exhaustive testing
Apply all possible input combinations to CUD
A complete functional testing
100% coverage on all possible faults
Limitation
Only applicable for circuits with medium number of
inputs
6-stage
LFSR
Circuit Under Test
(CUD)
Signature
Analyzer
(SA)
41
Pseudo Exhaustive Testing
(PET)
Apply all possible input combinations to every
partitioned sub-circuits
100% fault coverage on single faults and multiple
faults within the sub-circuits
Test time is determined by the number of sub-
circuits and the number of inputs to the sub-circuit
Partitioning is a difficult task
Cone Segmentation
Sensitized-Path Segmentation
Physical Segmentation
Use DFT circuits to aid partitioning
42
Example for Cone Segmentation
2*2
5
=64vectors are enough to pseudo-exhaustively test this circuit,
Compared to 2
8
=256 vectors for naive exhaustive testing
43
Example for Sensitized-Path
Segmentation
C1
C2
C
D
Testing procedure
Apply input pattern X2 such that D=0
Apply exhaustive patterns to C1
Apply input pattern X1 such that C=0
Apply exhaustive patterns to C2
X1
X2
44
Outline
Basics
Test Pattern Generation
Response Analyzers
How to compress the output response without
losing too much accuracy
BIST Examples
45
Why Compaction ?
Motivation
Bit-to-bit comparison is infeasible for BIST
Compaction
Compress a very long output sequence into a single
signature
Lossy compression
Signature analysis: Compare the compressed word
with the pre-stored gold signature to determine the
correctness of the circuit
Problems
Many output sequences may have the same signature
after the compression leading to the aliasing problem
46
Lossy Compression V.S.
Coding
We want to sort inputs into different groups
Inputs of our problem: 1 million 32 bit responses from circuits
Different inputs are put into the same code as fault free one
Total input space
code word 1
(Fault free)
code word 2
code word i
code word N
47
Test Response Compaction
Techniques
The signature & its collection algorithm should meet
the following guideline:
1. The algorithm must be simple enough
To be implemented as part of the built-in test circuitry.
2. The implementation must be fast enough
To remove it as a limiting factor in test time.
3. The compression method should minimize the loss of
information.
Minimize the aliasing, i.e., loss of evidence of a fault indicated by
a wrong response from the circuit under test.
Circuit
Under
Test
T
P
G
Compactor
Signature
output
response
48
Signature Analysis by LFSR
Procedure
Apply predetermined patterns
Divide the output sequence by LFSR
Test
Pattern
CUT LFSR
49
LFSR for Polynomial Division
Suppose we are interested in modulo 2 division.
P(x)/G(x) =(x
7
+x
3
+x)/(x
5
+x
3
+x+1)
The longhand division can be conducted in
terms of the detached coefficients only:
101 Q(x)=x
2
+1
101011
10001010
101011
00100110
101011
001101=R R(x)=x
3
+x
2
+1
This division process can be mechanized using a LFSR.
50
Galois Field GF(2)
Operation
Modulo-2 addition, subtraction, multiplication, and
division of binary data
Properties
Modulo-2 addition and subtraction are identical
0+0=0, 0+1=1, 1+0=1, 1+1=0
0-0=0, 0-1=1, 1-0=1, 1-1=0
Bit-stream
multiplication
Bit-stream
division
51
When a shift occurs, x
5
is replaced by x
3
+x
1
+x
0
.
Thus, whenever a quotient coefficient(the x
5
term) is shifted off the right-most stage,
x
3
+x
1
+x
0
is added to the register (or subtracted
from the register since addition is the same as
subtraction modulo 2). Effectively, the dividend
has been divided by x
5
+x
3
+ x+1.
+
Ex: LFSR implementing division by
f(X)=x
5
+x
3
+x+1
+ +
x
0
x
1
x
2
x
3
x
4
input
52
If the LFSR is initialized to zero & the
message word (or dividend) P(x) is serially
streamed to the LFSR input, high-order
coefficient first, the content of the LFSR after
the last message bit is the remainder from
the division of the message polynomial by
the divisor G(x).
53
Example: P(x)=x
7
+x
3
+x input=10001010
+ + +
x
0
x
1
x
2
x
3
x
4
input
x
5
Remainder R=x
3
+x
2
+1 Quotient
Q=x
2
+1
input
time
0
1
2
3
4
5
6
7
8
1
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
54
Any data, such as the test response results
from a circuit, can be compressed into a
code word by an LFSR.
This code word, the remainder from the
division process, is called the signature of
the input data stream.
The LFSR itself is called a signature
analyzer.
P(x)=Q(x)G(x) + R(x)
divisor signature
(LFSR polynomial)
55
If P(x) is the polynomial of the correct data
=> P(x)=P(x)+M(x)G(x) will have the same
signature as P(x) for any M(x).
Example: P(x)=x
7
+x
3
+x
G(x)=x
5
+x
3
+x+1
signature R(x)=x
3
+x
2
+1
P(x)=P(x)+G(x)=x
7
+x
5
+1
P(x)=P(x)+xG(x)=x
7
+x
6
+x
4
+x
3
+x
2
P(x) and P(x) have same signature x
3
+x
2
+1.
Aliasing: condition in which a faulty circuit
with erroneous response produces the same
signature as a good circuit.
Aliasing probability is usually used to
measure the quality of a data compressor.
56
What is the aliasing probability of
using LFSR as a data compressor?
Suppose the input string is m-bit long. There are
2
m
-1 possible bit streams.
If the divisor polynomial G(x) is of degree r, then
it has 2
m-r
-1 nonzero multiples that result in a
polynomial of degree less than m.
=> There are 2
m-r
-1 wrong m-bit streams that
can map into the same signature as the correct
bit stream.
=> Aliasing prob. P(M)=(2
m-r
-1)/(2
m
-1)
=> For large m, P(M) 1/2
r
.
57
Comparison with other compression
methods
One count compression
The signature is the sum of the number of 1s
appearing on the circuit output during the test.
Suppose that the data to be compressed is
N-bit long and r is the expected ones count,
0<=r<=N.
P(M / r ) = == =
N
r
| || |
\ \\ \

| || |

| || |
1
2
N
1
Ex: N=7
r P(M/r)
0 0
1 .047
2 .157
3 .268
4 .268
5 .157
6 .047
7 0
58
Transition-Counting Signature
Procedure
Apply predetermined patterns
Count the number of 01 and 10 transitions
Test
Pattern
CUT
Counter
Clock
DFF
Transition count
59
Aliasing of Transition-
Counting
Consider a sub-sequence of bits
( r
j-1
r
j
r
j+1
)
If r
j-1
is not equal to r
j+1
, then an error occurring at r
j
will not be detected by transition counting.
Example
1. (0, 1, 1) (0, 0, 1)
2. (0, 0, 1) (0, 1, 1)
3. (1, 1, 0) (1, 0, 0)
4. (1, 0, 0) (1, 1, 0)
60
Transition count compression
The signature in transition count testing is the
number of logical transitions ( 0->1 & 1->0 ) in
the data stream.
Assume the data streams length is N and a
transition count = i
P(M / i ) = == =
2
N 1
i
| || |
\ \\ \

| || |

| || |
1
2
N
1
i P(M/i)
0 0.00787
1 .0866
2 .228
3 .307
4 .228
5 .0866
6 .00787
Ex: N=7
Low aliasing probability when i is small or large
61
LFSR:
Ex: m=3 P(M) 0.125
m=4 P(M) 0.0625
m=5 P(M) 0.03125
P(M) =
2
N m
1
2
N
1
62
Multiple-Input Signature Register
(MISR)
For built-in testing of multiple-output circuits, the
overhead of a single-input signature analyzer on
every output would be high.
A multiple-input signature register (MISR) is
used for multiple-output circuits.
+ + + + +
I
0
I
1
I
2
I
3
I
4
C U T
63
It can be proved that the aliasing
probability of a MISR is:
(2
n-1
-1)/(2
m+n-1
-1) 1/2
m
m: the number of stages in MISR
n: length of data to be compressed.
Ref: Built-In Test for VLSI, Chapter 5, Paul H.
Bardell et al, 1987.
64
Improving Signature Analysis
Increase the length of LFSR
Repeat test using different feedback structure of
LFSR
Repeat test using different orders of vectors
Multiple observation on signatures
65
Outline
Basics
Test Pattern Generation
Response Analyzers
BIST Examples
66
Pseudo Random Testing
Hardware
Combinational
LFSR
Combinational
circuit
SA
Sequential
LFSR
Combinational
circuit
SA
Fault coverage could be low
67
BIST Pseudo Random
Testing Hardware
Circuit Under Test
Shift register
10-stage
LFSR
SA
(CEBT)
LFSR
SA
S
R
S
R
S
R
CUT CUT
(STUMPS)
test-per-clock configuration test-per-scan configuration
68
Built-In Logic Block
Observation (BILBO)
0
1
M
U
X
Z
1
Q D
Q
Q
1
Z
2
D
Q
Q
Q
2
...
...
...
Q D
Q
Q
n-1
Z
n
D
Q
Q
Q
n
...
S
i
B
2
B
1
B
1
B
2
operation mode
0 0 shift register
0 1 LFSR pattern generation
1 1 MISR response compressor
1 0 parallel load (normal operation)
scan-in
Scan-out
69
Example: BILBO-Based BIST
Test procedure
each logic block C1, C2, C3 are tested in a serial manner
BIST controller needs to configure each BILBO registers
properly during self-testing
C
1
BILBO1
BILBO2
C
2
BILBO3
C
3
when testing C1
BILBO1 is a PRPG
BILBO2 is a MISR
70
Concurrent BILBO
BILBO
C1
Operate as PRPG and
MISR simultaneously
Logic with self-loop
top-row of D-FFs MISR
bottom-row of D-FFs PRPG
concurrent BILBO
B1 B2 Operation
mode
- 0 Normal
1 1 Scan
0 1 PRPG/MISR
1
0
M
U
X
Z
1
Q D
Z
2
D Q
...
...
...
...
S
i
B
1
scan-in
Q D1
Q
Q
1
Q
D2
Sel
Q D1
Q
Q
2
D2
Sel
B
2
71
STUMPS Architecture
multiple input signature register
pseudo-random pattern generator
c
h
a
i
n

4
c
h
a
i
n

2
c
h
a
i
n

3
c
h
a
i
n

1
primary
input pins
primary
output pins
Self-Test Using a MISR and Parallel Shift register sequence generator
Saving some hardware by reducing LFSR/MISR, but increase test time
Require PIs and POs to be caught by some scan chain
72
Comparison of BILBO, STUMPS,
and External ATE
P=2000,000
ATE operate at 325MHz
L=scan chain length=100bit
CP=clock period
K=ATE speed/clock period
BILBO STUMPS ATE
Test time
(CP=1/325MHz)
PxCP
0.00615s
PxLxCP
0. 615s
PxLxCPxK
0. 615s
(K=1)
Test time
(CP=1/1GHz)
PxCP
0.002s
PxLxCP
0.2s
PxLxCPxK
0. 615s
(K=3)
P can be much
smaller than BIST
Scan clock do
not scale well as
K
STUMPS is still limited
by scan clocks, unless
scan enable is locally
controlled per chain.
73
Comparison of BILBO,
STUMPS, and External ATE (II)
P=2000,000; P1=20000
ATE operate at 325MHz
L=scan chain length=100bit
CP=clock period; CP1=1/(10M)
K=ATE speed/clock period
BILBO STUMPS ATE
Test time
(CP=1/325MHz)
PxCP
0.00615s
PxLxCP
0.615s
P1xLxCP1
0. 2s
Test time
(CP=1/1GHz)
PxCP
0.002s
PxLxCP
0.2s
P1xLxCP1
0. 2s
74
LBIST with SGL Architecture
75
SGL Logics
76
LBIST Statistics
Source: Application of Deterministic Logic BIST on Industrial Circuits
JOURNAL OF ELECTRONIC TESTING: Theory and Applications 17, 351362, 2001