24C64 BM
24C64 BM
24C64 BM
Bookly Micro
JANUARY 2007
DESCRIPTION
The 24C32 and 24C64 are electrically erasable PROM devices that use the standard 2wire interface for communications. The 24C32 and 24C64 contain a memory array of 32Kbits (4K x 8) and 64K-bits (8K x 8), respectively. Each device is organized into 32 byte pages for page write mode. This EEPROM operates in a wide voltage range of 1.8V to 5.5V to be compatible with most application voltages. designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are available in 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, 8-pad DFN, and 8-pin MSOP packages. The 24C32/64 maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The 24CXX has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.
Copyright 2007 Bookly Micro, Inc. All rights reserved. BM reserves the right to make changes to this specification and its products at any time without notice. BM assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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Rev. B 01/09/07
24C32 24C64
Bookly Micro
Vcc 8
X DECODER
SCL 6
CONTROL LOGIC
EEPROM ARRAY
Y DECODER
GND 4 nMOS
ACK
Clock DI/O
>
DATA REGISTER
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Rev. B 01/09/07
24C32 24C64
PIN CONFIGURATION 8-Pin DIP, SOIC, TSSOP, and MSOP
Bookly Micro
A0 A1 A2 GND
1 2 3 4
8 7 6 5
PIN DESCRIPTIONS
A0-A2 SDA SCL WP Vcc GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply Ground
SCL
This input clock pin is used to synchronize the data transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that are hardwired or left not connected for hardware compatibility with the 24C16. When pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system. When the pins are not hardwired, the default values of A0, A1, and A2 are zero.
WP
WP is the Write Protect pin. The input level determines if all, partial, or none of the array is protected from modifications.
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Rev. B 01/09/07
24C32 24C64
Bookly Micro
Stop Condition
The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition.
DEVICE OPERATION
24CXX features serial communication and supports a bidirectional 2-wire bus transmission protocol called I2CTM.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is controlled by a Master device that generates the SCL, controls the bus access, and generates the Stop and Start conditions. The 24CXX is the Slave device on the bus.
Acknowledge (ACK)
After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line.
Reset
The 24CXX contains a reset function in case the 2wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The 24CXX will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if a no write operation is initiated; or c) Following any internal write operation.
Start Condition
The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met.
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Rev. B 01/09/07
24C32 24C64
DEVICE ADDRESSING
The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits. The four most significant bits of the Slave address are fixed as 1010 for the 24CXX. The next three bits of the Slave address are A0, A1, and A2, and are used in comparison with the hard-wired input values on the A0, A1, and A2 pins. Up to eight 24CXX units may share the 2-wire bus. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg.24C64) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected EEPROM then prepares for a Read or Write operation by monitoring the bus.
Bookly Micro
WRITE OPERATION Byte Write
In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the two byte address that is to be written into the address pointer of the 24CXX. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The 24CXX acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.
Page Write
The 24CXX is capable of 32-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 31 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the five lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 32 bytes prior to issuing the Stop condition, the address counter will roll over, and the previously written data will be overwritten. Once all 32 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the 24CXX in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.
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Rev. B 01/09/
24C32 24C64
READ OPERATION
Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to 1. There are three Read operation options: current address read, random address read and sequential read.
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Random Address Read
Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the 24CXX acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the 24CXX sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the 24CXX. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1, n+2 ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of 8191 for 24C64 or 4095 for 24C32 (depending on the device) is reached, the address counter rolls over to address 0, and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram).
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Rev. B 01/09/07
24C32 24C64
Figure 1. Typical System Bus Configuration
Vcc
Bookly Micro
SDA SCL
Master Transmitter/ Receiver
24CXX
ACK
STOP Condition
SDA
START Condition
SCL
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Rev. B 01/0 9/07
24C32 24C64
Figure 4. Data Validity Protocol
Bookly Micro
Data Change
SCL
Data Stable Data Stable
SDA
BIT
A2
A1
A0
R/W
Device Address
M S B
Word Address Word Address A A A C * * * # C C K K K L M S * = Don't care bits S B B # = Don't care bit for 24C32 R/W
Data
Device Address
Data (n) A C K
Data (n+1) A C K
Data (n+31) A C K
S T O P
M S B
L S B R/W
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Rev. B 01/09/07
24C32 24C64
Figure 8. Current Address Read
S T A R T SDA Bus Activity M S B L S B
R/W
Bookly Micro
Device Address
R E A D A C K
Data
S T O P
N O A C K
Device Address
Device Address
R E A D
Data n A C K
N O
S T O P
L S B R/W
A C K
DUMMY WRITE
Data Byte n A C K A C K
S T O P
N O
R/W
A C K
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Rev. B 01/09/07
24C32 24C64
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value 0.5 to +6.5 0.5 to Vcc + 0.5 55 to +125 65 to +150 5 Unit V V C C mA
Bookly Micro
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
10
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Rev. B 01/09/0