PCIRF 3 1 Layout
PCIRF 3 1 Layout
PCIRF 3 1 Layout
MOS Fabrication Sequence CMOS Design Rules Layout Techniques Layout Examples
Reference Material
Razavi Chapter 17 & 18
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N-Well
Substrate is always connected to the most negative voltage, and is shared by all N-type transistors
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Front-End Back-End A silicide step, where highly conductive metal is deposited on the gate and diffusion regions, reduces transistor terminal resistance To prevent potential gatesource/drain shorting an oxide spacer is first formed before silicide deposition
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Transistor Geometries
-based design rules allow a process and feature sizeindependent way of setting mask dimensions to scale
Due to complexity of modern processing, not used often today
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Assume w.c. mask alignment <0.75 Relative misalignment between 2 masks is <1.5
AGate = W * L AD, AS = W * X PS , PS = W + 2 X (3 sides)
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P-channel MOSFET
Drain Metal 1 CVD Oxide Source
Polysilicon Layer 1 Polysilicon Layer 2 P+ Ion Implant N+ Ion Implant Contact cut to n+/p_ Metal 1 Via Oxide Cuts Metal 2 Pad Contact (Overglass)
n+
p+ Gate Oxide n-well Bulk p substrate Bulk p+
N-channel MOSFET
Source Metal 1 CVD Oxide Drain Poly Gate Gate Oxide p substrate Bulk
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n+
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Metal n+
n+
Implanted dopants p, Na
p, Na
Depletion regions
n+ Nd
n+
p, Na
Nselect
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Active
Poly gate
W
Nselect
Active
n+ p-Substrate
n+ p-Substrate
Poly gate Poly gate
Poly gate
substrate
substrate
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Mask Number 1 2 3 4 5 6 7 8 9 10 11
SELECT POLY CONTACT ACTIVE CONTACT METAL1 VIA METAL2 PAD POLY2
n+
L
Side View
n+
FrontView
Difference between the drawn and physical values for channel length and the channel width
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L'
n+
Field oxide
n+ p
Bulk
2
n+/p+
2 or 3
Often, we use a use a slightly larger minimum that is equal to the contact height (4 in this example)
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N-channel MOSFET
Metal 1 CVD Oxide Drain Poly Gate n+ Gate Oxide p substrate Bulk
Gate
P-channel MOSFET
Drain Metal 1 CVD Oxide
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Source
n+
p+
p+
Gate
Source Bulk
Source Bulk
n-well
n+
Poly
n+
n+
Poly
n+
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Stick Diagrams
D
(a) Definitions
(b) MOSFET
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Wp
Lp
N-Well
p+
Poly In nFET
WN
n+
WN
LN
Wp
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Out
A MnA
n+
Metal VDD
MpA
pFET p+
MpB
Vo A B MnA MnB
Out nFET
Metal GND
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Transistor orientation
Orientation is important in analog circuits for matching purposes
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Stacked Transistors
Wide transistors need to be split Parallel connection of n elements (n = 4 for this example) Contact space is shared among transistors Parasitic capacitances are reduced (important for high speed )
Drain
Gate Source Note that parasitic capacitors are lesser at the drain
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Matched Transistors
Simple layouts are prone to process variations, e.g. VT, KP, Cox Matched transistors require elaborated layout techniques
M1
M2
Process Variations
Drain M1
Drain M2
Source
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Interdigitized Layout
Averages the process variations among transistors Common terminal is like a serpentine
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Why Interdigitized?
M1
M2
M2
M1
M1
M2
M2
M1
KP=1
KP2
KP3
KP4
KP5
KP6
KP7
KP8
Process variations are averaged among transistors KPs for M1: KP1+KP4+KP5+KP8 M2: KP2+KP3+KP6+KP7 Technique maybe good for matching dc conditions Uneven total drain area between M1 and M2. This is undesirable for ac conditions: capacitors and other parameters may not be equal A more robust approach is needed (Use dummies if needed !!)
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Each transistor is split in four equal parts interleaved in two by twos. So that for one pair of pieces of the same transistor we have currents flowing in opposite direction. Transistors have the same source and drain area and perimeters, but this topology is more susceptible to gradients (not common centroid) 25
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M2 M1 M2 M1
M1 M2 M1 M2
M2 M1 M2 M1
CENTROID (complex layout) M1: 8 transistors (0,3) (0,1) (1,2) (1,0) (2,3) (2,1) (3,2) (3,0) M2: 8 transistors (0,2) (0,0) (1,3) (1,1 (2,2) (2,0) (3,3) (3,1)
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Many contacts placed close to one another reduces series resistance and make the surface of metal connection smoother than when we use only one contact; this prevents microcraks in metal; Splitting the transistor in a number of equal part connected in parallel reduces the area of each transistor and so reduces further the parasitic capacitances, but accuracy might be degraded!
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Diffusion resistors
Diffused resistance
Diffused resistance
well resistance
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Integrated Resistors
Highly resistive layers (p+, n+, well or polysilicon) R defines the resistance of a square of the layer Accuracy less than 30%
Current flow Resistivity (volumetric measure of materials resistive characteristic)
L t W
(-cm)
L
Sheet resistance (measure of the resistance of a uniform film with arbitrary thickness t
R = /t (/)
W L
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R = 2Rcontact + (L/W) R
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L + R W
Sheet Resistance W/0 30 - 50 50 -150 2K - 4K 3K - 6K 6K - 10K 9K - 13K 20 - 40 15 - 40 Accuracy % 20 - 40 20 - 40 15 - 30 15 - 30 25 - 40 25 - 40 25 - 40 25 - 40
W L
Temperature Coefficient ppm/oC 200 - 1K 200 - 1K 5K 5K 10K 10K 500 - 1500 500 - 1500
Special poly sheet resistance for some analog processes might be as high as 1.2 K/
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Large Resistors
In order to implement large resistors : Use of long strips (large L/W) Use of layers with high sheet resistance (bad performances)
L L R= R = W W xj
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Well-Diffusion Resistor
Example shows two long resistors for K range Alternatively, serpentine shapes can be used Noise problems from the body Substrate bias surrounding the well Substrate bias between the parallel strips
Dummies
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uncompensated
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Etching
Wet etching : isotropic (undercut effect) HF for SiO2 ; H3PO4 for Al x for polysilicon may be 0.2 0.4 m with standard deviation 0.04 0.08 m. Reactive ion etching (R.I.E.)(plasma etching associated to bombardment) : unisotropic. x for polysilicon is 0.05 m with standard deviation 0.01 m Boundary : The etching depends on the boundary conditions Use dummy strips
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Impact of Rcont depends on relative geometry Best to always use a resistor W that is at least as large as the contact
Interdigitized structure :
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Poly Resistors
First polysilicon resistance
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Electrodes : metal; polysilicon; diffusion Insulator : silicon oxide; polysilicon oxide; CVD oxide
C=
ox t ox
2
WL
2 t ox C r + = C r t ox
TOP VIEW
L 2 W 2 + + L W
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Oxide damage Impurities Bias condition Bias history (for CVD) Stress Temperature
ox ox
t ox t ox
Etching Alignment
L W ; L W
C 1 0.1% C
C r = C r
2
t ox + t ox
L W + + L W
2
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Note, the absolute C may vary as high as 20% due to process variations
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Poly 2 Poly 1 Area is determined by poly2 Problems undercut effects nonuniform dielectric thickness matching among capacitors Minimize the rings (inductors)
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Unit capacitors are connected in parallel to form a larger capacitance Typically the ratio among capacitors is what matters The error in one capacitor is proportional to perimeter-area ratio Use dummies for better matching (See Johns & Martin Book, page 112)
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C1 TC1
C2 TC2
C3 TC3
C4 TC4
C5 TC5
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Floating Capacitors
Be aware of parasitic capacitors
poly2 CP1 poly1 C1 CP2 substrate C1 CP1 CP2 metal2 CP1, CP2 are very small (1-5 % of C1) CP2 is around 10-50 % of C1 CP2
Polysilicon-Polysilicon: Bottom plate capacitance is comparable (10-30 %) with the poly-poly capacitance
Metal1-Metal2: More clean, but the capacitance per micrometer square is smaller. Good option for very high frequency applications ( C~ 0.10.3 pF).
Thick oxide
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Typical Capacitance Process Data (See MOSIS webside for the AMI 0.6 CMOS process)
Capacitance Area (substrate) Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Fringe (substrate) Fringe (poly) N+Actv P+Actv Poly 292 290 35 1091
1072
900
80 170
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Potential for parasitic BJTs (Vertical PNP and Lateral NPN) to form a positive feedback loop circuit If circuit is triggered, due to current injected into substrate, then a large current can be drawn through the circuit and cause damage Important to minimize substrate and well resistance with many contacts/guard rings
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ECEN-474-2009
Jose Silva-Martinez
M1 and M2 must match. Layout is interdigitized M3 and M4 must match. M6 must be wider by 4*M3 M7 must be 2*M5 Layout is an interconnection of 3 stacks; 2 for NMOS and 1 for PMOS Capacitor made by poly-poly
Not the best floorplan
M3 M6 M6 M6 M6 M4
M3
M4 M6
M1
M2 M8 M5 M7
M1
M2
M1
M2
M1
M2
M5
M7
M7
M7
M7
M5
M8
Pay attention to your floor plan! It is critical for minimizing50iterations: Identify the critical elements
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2 4
1 3
Figure: Layout of a single stage fully differential amplifier and its CMFB circuit. 54 1. I/p NMOS diff pair 2. PMOS (Interdigitated) 3. Resistors for VCM 4.Capacitors (Common centroid)
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Resistive network
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3-bit quantizer in Jazz 0.18m CMOS technology S/H: sample-and-hold circuit that is used to sample the continuous-input signal Core: contains matched differential pairs and resistors to create accurate reference levels for the analog-todigital conversion 56 Latches: store the output bits; provide interface to digital circuitry with rail-to-rail voltage levels
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High-speed D-Flip-Flop in Jazz 0.18m CMOS technology Resolves a small differential input with 10mV < Vp-p < 150mV in less than 360ps Provides digital output (differential, rail-to-rail) clocked at 400MHz The sensitive input stage (1st differential pair) has a separate analog supply line to isolate it from the noise 57 on the supply line caused by switching of digital circuitry
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Overall amplifier: Have a look on the guard rings and additional well! 59
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BIAS: you may be able to see the dummies, symmetry and S/D connections 60
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