1.

Basics concepts of VLSI

1.1 List the different process of MOS transistor fabrication :
fabrication process of MOS transistors :
1. PMOS fabrication process
2. NMOS fabrication process
3. CMOS fabrication process
I) the p-well process
ii) the n-well process
iii)the twin tub process
4. BiCMOS fabrication process
1.2 List the merits of CMOS technology:
1. low static power dissipation
2. high input impedance (low drive current)
3. scalable threshold voltage
4. high noise margin
5. high packing density
6. high delay sensitivity to load(fan out limitation)
7. low output drive current
8. low gm(gm α vin)
9. Bidirectional capacity ( drain and source are interchangeable )
10. A near ideal switching device
1.3 Explain CMOS fabrication process:
CMOS FABRICATION
There are a number of approaches to CMOS fabrication, including
The p-well,
The n-well,
The twin-tub,
The Silicon on insulator processes.
The P-well Process
A brief overview of the fabrication steps may be obtained with reference to figure below
  The pwell process structure consists of an n-type substrate in which p-devices maybe formed by suitable
masking and diffusion. In order to accommodate n-type devices, a deep p-well is diffused into the n-type
substrate as shown.
 This diffusion must be carried out with special care since the p-well doping concentration and depth will
affect the threshold voltages as well as the breakdown voltages of the n-transistors.
 To achieve low threshold voltages (0 .6 to 1.0 V) either deep-well diffusion or high-well resistivity is
preferred. However, deep wells require larger spacing between the n- and p-type transistors and wires due
to lateral diffusion and therefore a larger chip area.
 The p-wells act as substrates for the n-devices within the parent n-substrate, and, provided
that voltage polarity restrictions are observed, the two areas are electrically isolated. However, since there are now
in effect two substrates, two substrate connections ( VDD and Vss) are required, as shown in figure below

In all other respects-masking, patterning, and diffusion-the process is similar to nMOS fabrication.
Typical processing steps are:
 Mask 1 - defines the areas in which the deep p-well diffusions are to take place.
 Mask 2 - defines the thin oxides regions, namely those areas where the thick oxide is
to be stripped(remove all covering from) and thin oxide grown to accommodate p- and n-transistors and wires.
 Mask 3 - used to pattern the polysilicon layer which is deposited after the thin
oxide.
 Mask 4 - A p-plus mask is now used to define all areas where p-diffusion is to take place.
 Mask 5 - This is usually performed using the negative form of the p-plus mask and
defines those areas where n-type diffusion is to take place.
 Mask 6 - Contact cuts are now defined.
 Mask 7 - The metal layer pattern is defined by this mask.
 Mask 8 - An overall over glass layer is now applied and Mask 8 is needed to define for access to bonding
pads.
The N- well process:
N-well fabrication has also gained wide acceptance .
N-well CMOS circuits are also superior(high in rank) to p-well because of:
 The lower substrate bias effects on transistor threshold voltage.
 Lower parasitic capacitances associated with source and drain regions.
 Latch-up problems can be considerably reduced by using a low-resistivity epitaxial p-type substrate as the
starting material, which can subsequently act as a very low resistance ground-plane to collect substrate currents.
However, a factor of the n-well process is that the performance of the already poorly performing p-transistor is
even further degraded.
Modern process lines overcoming these problems and achieving, and good device performance may be achieved
for both p-well and n-well fabrication
The Twin-Tub Process:
Logical extension of the p-well and n-well approaches is the twin-tub fabrication process.
Here we start with a substrate of high resistivity n-type material and then create both n-well and p-well regions.
the foundation can be of any type substrate that acts as a neutral substrate .this process is more flexible but
complicated to build .
This is particularly important as far as latch-up is concerned.
In general, the twin-tub process allows separate optimization of the n- and p-transistors.
1.4 List layout design rules:
 Design rules represents the power which see very high chance of correct fabrication.
• Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in silicon
• Provides Interface between circuit designer and fabrication engineer
Design Rules
The design rules mainly 2 types

1.lambda based design rules

 contact cuts rules
 double metal MOS process rules
 CMOS lambda based design rules
2. Micron Based Rules
 2μm double metal double poly CMOS/BICMOS rules
 1.2μm double metal single poly CMOS
3.General observation on the design rules
1.5 Explain layout design rules:
Lambda-based Design Rules:
• Lambda-based (scalable CMOS) design rules define scalable rules based on .
• Circuit designer in general want tighter, smaller layouts for improved performance and decreased silicon
area. On the other hand, the process engineer wants design rules that result in a controllable and
reproducible process.
• Generally there has to be a compromise for a competitive circuit to be produced at a reasonable cost.
• All widths, spacing, and distances are written in the form λ
• For n-diffusion minimum width is 2λ and spacing between 2 n-diffusion layers is 3λ.
• Width of metal 1 is 3λ and the spacing between metal 1 and metal 2 is 3λ. and some of the measuring width
and spacing is mentioned in diagram.
• minimum size of well is 12λ
• minimum well to well spacing is 11λ
• minimum surface area of the well is 144λ
Merits:
• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out mask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2 λ
 • Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted

Contact Cuts
When making contacts between poly silicon and diffusion in nMOS circuits it should be recognized that there are
three possible approaches—
1. poly. to metal then metal to diffusion.,
2. buried contact poly silicon. to diffusion.,
3. butting contact (poly silicon. to diffusion. using metal).
 The buried contact is the most widely used, giving economy in space and a reliable contact. Butting contacts
were widely used at one time but mostly buried contacts are included in the figures for the completeness.
 In CMOS designs poly to diffusion contacts are almost made via metal
 when making connections between metal and either of the other 2 layers the process is quit simple ,the 2
x 2 contact cut indicates an area in which the oxide is to be removed down to the underlying(involving basic
facts) poly silicon or diffusion surface. When deposition of the metal layer takes place the metal is deposited
through the contact cut areas onto the underlying area so that contact is made between the layers

Butting contact: When connecting diffusion to poly silicon using the butting contact approach the process is
rather more complex. In effect, a 2 x 2 contact cut is made down to each of the layers to be joined. The layers
are butted together in such a way that these two contact cuts become contiguous (pakka pakka).
Buried contact: Basically, layers are joined over a 2 x 2 area with the buried contact cut extending by 1 in all
directions around the contact area except that the contact cut extension is increased to 2 in diffusion paths
leaving the contact area. This is to avoid forming unwanted transistors.

Double Metal MOS Process Rules

Double Metal Process is convenient & Provide a greater degree of freedom in layout drawing.
1. Metal 2 is used for the global distribution of power buses, that is VDD & GND(Vss) , and for clock lines.
2. Metal1 is used for local of power and for signal lines.
3. Lay out the two metal Layers so that conductors are mutually orthogonal wherever possible.
Metal2 is in Dark blue( or Purple) color.
Usually second level metal layers are rudeness (than the first. Isolation between the layers may also be of relatively
greater thickness.
The contacts between metal2 and metal1 are called as Vias.

CMOS LAMBDA BASED DESIGNED RULES:

The rules for n-well ,p- wires and special substrate contacts are added to the existing NMOS rules the rules are
readily translated to an n-well process. Although CMOS rules in total seen difficult to comprehend(grahimchatam)
for new designer once has been made of simpler NMOS rules the translation to CMOS is not hard to achieve
GBNERAL OBSERVATIONS ON THB DESIGN RULES
 A major problem is presented by possible deviation in line widths and in interlayer registration.

 If the line widths are too small, it is possible for lines thus defined to be discontinuous in places.
 If separate paths in a layer are placed too close together, it is possible that they will merge in places or
interfere with each other.
 The goal of any set of design rules should be to optimize yield(refers to the percentage of defect
free(usable) die on a silicon wafer) while keeping the geometry as small as possible without compromising the
reliability of the finished circuits
 may be viewed as a bound on the width deviation of a feature from its ideal 'as drawn' size and also as a
bound on the maximum misalignment of any one mask. In the worst case, these effects may combine to cause the
relative position of feature edges on different mask levels to deviate by as much as 2 in their interrelationship.
Inevitably(sure to occur), a consequence (the effcet)of using the lambda-based concept is that every dimension
must be rounded up to whole  values and this leads to layouts which do not fully exploit the capabilities of the
process.
Similar concepts underlie the establishment of 'micron-based' rule sets, but actual dimensions are given so that
full advantage can be taken of the fabrication line capabilities and tighter layouts result.
Micron Based Rules (2µ MOS Process):
 The monochrome encode rules set for the orbit 2μm double metal double poly ,Bicmos process is given
below
 the n-diffusion width is 3μm and spacing between 2 n-diffusion layers are 2.5μmthye color coding is used
to indicate the polysilicon layers that is red and p-diffusion color is yellow the difference between 2
polysilicon layers is 2.5μm

1.6 explain stick diagrams:

STICK DIAGRAMS
A VLSI circuit may be viewed as a 3-dimensional set of patterned material layers. Stick diagrams provide a
top view of the patterns. A stick diagram can be thought as a simplified version of layout. Stick diagrams are
useful for planning the layout and routing of integrated circuits. In a stick diagram, every line of a conducting
material layer is represented by a line of a distinct colour. The colour allows us to trace signal flow paths through
the conducting layers in a distinct colour. The colours allow us to trace signal flow paths through the conducting
layers in a complex integrated circuit. Planning a physical design using stick diagrams before going to CAD tool
can save lot of time and energy.

• Stick diagrams are a means of capturing topography (the detailed mapping) and layer information using
simple diagrams.
• Stick diagrams convey layer information through color codes (or monochrome encoding).
• Acts as an interface between schematic circuit and the actual layout.
• Does show all components/vias.
• Via is used to connect higher level metals from metal connection
• It shows relative placement of components.
• Goes one step closer to the layout & Helps plan the layout and routing
Limitations:
• Does not show
– Exact placement of components
– Transistor sizes

– Wire lengths, wire widths, tub boundaries

– Any other low level details such as parasitic
 –

Fig. Encodings for a simple metal nMOS process

 1.7 Explain VLSI design flow:
The idea may be used for a very specific application , and therefore want to develop an ASIC .that idea need
to convert in to detailed specifications

fig: VLSI design flow

Design Specifications:
The Specifications to be mentioned in a VLSI Design are as follows
1. The algorithm to be implemented in detail with mathematical representation.
2. Number of inputs and outputs in the design and number of bits in each of them
3. Number of bits used in the internal arithmetic operations.
4. Number of clock signals to be used in the design.
5. Maximum clock frequency to be used.
6. Area of the chip.
7. Power dissipation of the chip.
FRONT END DESIGN:
The logic design step is called as front end process and physical design can be called as back end process
Design Entry: Based on the specifications behavioral description is created to analyze the design in terms of
functionality and performance this behavioral descriptions are written in HDL ,such as verilog or very high speed
integrated circuits hardware description language (VHDL) to covert the specifications in to a chip. Design entry is
of two types: (a) Schematic Entry (b) Hardware Description Language (HDL) Entry. In Schematic Entry circuit
schematics are draw on schematic sheets using Graphical User Interface (GUI). In Schematic entry hierarchical
design is approached.
A Hardware Description Language (HDL) is similar to a typical computer programming language except that an
HDL is used to describe hardware rather than a program to be executed on a computer

Functional verification: The specifications / design written in HDL are block diagram is checked for syntax and
the simulation is done on desktop computer or work station. the next step is to verify the functionality of the design
by giving the necessary inputs and checking weather the correct output is obtained or not. The tool that performs
this task is called a functional simulator this is called functional verification.
synthesis: synthesis is done,which is process of translating the code in to a circuit (using gate and flip flops)and
optimizing the circuit to a ensure that the minimum number of gates are used and the timing constraints are met as
the wire lengths used inside the chip are a source of delays timing analysis as to be done on the entire internal
circuit.
Timing Simulation: An electronic circuit cannot perform its function instantaneously. When the values of inputs
to the circuit change, it takes a certain amount of time before a corresponding change occurs at the output. This is
called a propagation delays.

layout design: after the circuit design is functionally verified ,it is necessary to provide area efficient layout of the
circuit to generate the masks fabrication.
Planning Placement and Routing (PPR): Floor planning is the step to determine the shape of each sub-circuit
module and pin locations at their boundary and find out the approximate location of each module in a rectangular
chip. Placement is the problem of determination of best position of each module, when each module has a fixed
shape, area and terminals. Routing is the method of interconnections of different circuit components, with an aim
to minimize the chip area and also reduction of total wire-length.

Fabrication, Packing, and Testing: Fabrication requires many deposition, masking, etching and implant steps.
Processed wafers are sliced into die (chips) and packaged. Even tiny defects in a wafer or dust particles can cause
a chip to fail. Chips are tested before being sold. Testers capable of handling high-speed chips cost millions of
dollars, so many chips use built-in self- test features to reduce the tester time required. Then mask are prepared and
send to the fabrication unit where the chips are fabricated ,packaged , and shipped .
1.8 Explain VLSI design specifications and design entry:
Design Specifications:
(a) The algorithm to be implemented in detail with mathematical representation: The algorithmic specification
determines the complexity of the design and gives an idea of number of gates required for the design.
(b) Number of inputs and outputs in the design and number of bits in each of them: This specification takes
into account the type of interfacing to be used with the chip, e.g., for interfacing an analog to digital
converter, all data lines and control line inputs and outputs are provided in the chip. It also determines the
number of pins to be used in the chip.
(c) Number of bits used in the internal arithmetic operations: This is generally kept higher than the input bus
size in order to avoid chances of overflow and underflow and also to reduce the effect of accumulation of
round-off errors to maintain the required accuracy. In the hardware implementation of an arithmetic
intensive algorithm, the word lengths of resources such as adders, multipliers and registers has an algorithm
level optimization to meet the desired accuracy and minimization of design cost to meet a given
performance constraint.
(d) Number of clock signals to be used in the design: This is required because clock routing requires dedication
channels, which must be considered during fabrication of the chip. For a programmable type of pre-
fabrication IC’s, maximum number of clock signals can be used is predefined.
(e) Maximum clock frequency to be used: It defines the speed of operation of the chip. Maximization of
operating sped is one of the main objectives in VLSI design since faster operation needs lesser computation
time. If the chip interfaces with high speed devices, then the speed of operation of the chip becomes very
critical.

(f) Area of the chip: For portable type and miniature type of systems, chip size should be as small as possible.
Since million or more number of gates are incorporated on a single chip, so main optimization goal is area
of chip in IC design.
(g) Power dissipation in the chip: The demand for portable semiconductor devices has raised the demand for
more power efficient devices, due to the short battery life of these portable devices. Thus VLSI design has
also an objective of circuit level power saving by modifying circuit design such as reduction of switching
activity.
Design Entry:
In Design entry first of all architectural decision like number of sub-blocks to be used with their
functionality and interconnects such as adders, multipliers, dividers, type of processing, serial or parallel, in each
sub-blocks and whether the design will be pipelined, number of stages in the pipe-line and operation in each stage,
to be taken.
Design entries are of two types: (a) Schematic Entry (b) Hardware Description Language (HDL) Entry.
Schematic Entry: In Schematic Entry circuit schematics are draw on schematic sheets using Graphical User
Interface (GUI). Schematic library is available which consists symbols of basic gates and flip-flops that are termed
as primitive cells. The cells required to make a design are invoked on the sheet. Each cell dragged on the sheet is
given a specific instance name. Interconnections between components are done using nets for single bit-line and
buses for multiple bit-line and nets and buses are also given a name. Then the naming of inputs and outputs is done
A symbol can be created from the design with the same input and output naming convention and can be kept in the
cell library as a micro cell.
 In Schematic entry hierarchical design is approached. Large Design are divided in sub-designs are divided
in sub-designs, which may be further subdivided. The basic macro cells such as multiplexers, adders are designed
first and are kept in cell library. The higher sub-blocks are designed using the basic macro and primitive cells and
higher order macros can be designed and kept in cell library. The higher sub-blocks are designed using the basic
macro and primitive cells and higher order macros can be designed and kept in cell library. Thus the final design is
approached in a hierarchical manner.

Hardware Description Language (HDL) Entry: A Hardware Description Language (HDL) is similar to a typical
computer programming language except that an HDL is used to describe hardware rather than a program to be
executed on a computer. The two dominant hardware description languages that are used largely today are (i)
VHDL and (ii) Verilog HDL. Both languages are aimed at description digital hardware. A digital design can be
expressed in either structurally, in a data flow style or in a sequential behavior. Although the two languages differ
in many ways, the choice of using one or the other when studying logic circuits is not particular important, because

both offer similar features. In Verilog model, each variable can have maximum four values ‘0’,’1’,’x’,’z’. There
are two main data types on verilog net and register.

1.9 Explain functional simulation:

A circuit represented in the form of logic expressions can be simulated to verify that it will function as
expected. The tool that performs this task is called functional simulation. For schematic and HDL designs,
functional simulation is performed before design implementation to verify that the logic created is correct or not.
The design methodology determines when to perform functional simulation. Generally, for Schematic Flow
Projects, functional simulation is performed directly after completing design within the design entry tools. For
HDL Flow projects, functional simulation is performed after the design has been entered and synthesized.

There may be of two types of errors encountered in design entry: firstly the logic expressions derived for
implementing a function may be erroneous and secondly due to human error there may be unconnected nets, or
undue duplication of names in schematic entry or syntax error in HDL entry. For finding out whether there is an
error, and if it is, for detecting the location of error, stimulus is given at the input and output response is observed.
If output response complies with desired output, then it can be said that the design is functionally correct. If there
is a deviation, then location of error is found out by checking intermediate outputs. Then the design is corrected/
modified and re-verified.
 Stimulus at input can be design by using and editing waveform test vectors giving a pattern of 1 and 0’s to
the nets and for buses as a set of binary values like 1101, 0110 or in hexadecimal number system. Stimulus can
also be given through commands by using command file. The simulator display input and output waveforms
through waveform viewer after running the simulation. From the waveform viewer it can be verified visually that
the output response is correct or not. The output response can also be displayed in numeric form and also written in
a file for future reference. For debugging purpose intermediate test points are chosen and response from those
points is observed to detect the error. For functional simulation purpose gate delays and net delays are not taken
into account and logical functionality is only verified. The input and output waveform for the 2:1 MUX as
designed in schematic entry is shown below. When select input S is ‘0’ output is equal to A, otherwise B. So the
simulation verifies that the design is functionally correct. The waveform is shown in fig…………….

1.10 Explain Planning placement and Routing (PPR)

This part is referred as the VLSI physical design or layout phase. This is the process to determine the
physical location of devices and make interconnections between them inside the boundary of VLSI chip. Since the
cost of circuit fabrication increases in proportion with circuit area, so one of the main aims in layout phase is to
minimize the circuit area so that cost of chip is reduced. If chip area is smaller, it will have fewer defects also,
which in turn increases the yield. The other criteria to be fulfilled are wire length minimization, delay
minimization, power minimization, via minimization. Now-a-days there is an evolutionary development of

automated design process using Computer Aided design (CAD) tools. The various phases in layout process are as
follows.

1. Partitioning is the task of dividing a circuit in such a way so that area of each sub-circuit is well within
prescribed range and number of interconnections between sub-circuits is also minimized. In VLSI Physical
design, partitioning is the first step of solving a large problem by converting it to smaller sub-problem of
manageable size.

2. Floor planning is the step to determine the shape of each sub-circuit module and pin location at their
boundary and find out the approximate location of each module in a rectangular chip. The floor planning
has a similarity of building floor planning where the position of a set a rooms like dining room, kitchen,
drawing room in a house are placed based on some proximity criteria. A good floor planning aims to
reduce the chip area, make the subsequent routing proximity criteria. A good floor planning aims to reduce
the chip area, make the subsequent routing phase simpler and improve performance like signal delay
reduction.
 Fig: Example of floor planning fig: Example of placement fig: Example of routing
3. Placement is the problem of determination of best position of each module, when each module has a fixed
shape, area and terminals. Floor planning and placement are very closely related and sometimes combined
in a computer aided design automation process.
4. Routing is the method of interconnection of different circuit components, with an aim to minimize the chip
area and also reduction of total wire-length. Routing consists of a two step approach: Global routing is
done first and then followed by the channel routing.
The main aim of global routing is to develop a routing plan so that each net is assigned a particular
region. It partitions routing region to disjoint rectilinear sub regions and also gives an estimation of total
wire-length. Then detailed routing is done to effectively realize the interconnections. It takes each routing
region and assigns track to each net.
In detailed routing there are two kinds of rectilinear sub regions, channels and switch boxes.
Channels are routing regions having two parallel rows of fixed terminals. Switchboxes are generalized
channels having fixed terminals on all four sides of the region. The objective of a channel router is to
connect all the nets with minimum possible area. After planning placement and routing there is a possibility
that all components may not fit in a given chip size, or if they fit the design may not be routed. Then a few
iterations of planning, placement and routing is done to achieve successful routing. If it still fails, then
design entry is revisited by changing some parallel processing needs lesser components than
parallel processors. Thus the circuit components are reduced so that subsequent routing phase is easier.
1.11 Explain timing simulation
In function simulation done earlier only the functional/ logical correctness of the design is verified. But
after the design is fitted into the chip, net delays and gate delays come into account. Net delays are delays
encountered by a signal for traversing from outputs of one gate to the input of another gate. Gate delays are delays

from input of one gate to the output of same gate due to propagation time of the gate. Timing simulation is done
with the clock speed as per mentioned in design specification.
The procedure is similar to functional verification and input stimulus is given an output is verified. But a
functional correct design may fail in timing verification. Suppose data is fed to a sequential circuit from a purely
combinational circuit. But if the combinational path delay is greater than one clock period then data cannot be fed
to sequential circuit clock by clock.

Timing analysis is done to see the timing performance of a circuit such as set up and hold times of the flip-
flops are met. It gives a detailed report of all the gate delays and net delays of all the paths in the circuit to check
whether they meet the timing constraints of the design. It gives an idea of the maximum clock frequency can be
used for the given routed design.

If timing specifications is not fulfilled, then in first few iterations design is rerouted to achieve a design
with lesser delay. If rerouting fails then design is re-entered by changing some serial processors to parallel
processors in order to have a faster operations so that timing criteria is fulfilled. In a VLSI design there is a
tradeoff between the two criteria that is minimization of hardware requirements and maximization of clock speed
and a solution is arrived which optimally fulfill both requirements. If the design is more speed critical then area of
chip may be increased.

1.12 Explain the use of Verilog HDL in VLSI simulation

Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers many useful
features for hardware design.

1. Verilog HDL is a general-purpose hardware description language that is easy to learn and easy to use. It is
similar in syntax to the C programming language. Designers with C programming experience will find it
easy to learn verilog HDL.
2. Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a designer can
define a hardware model in terms of switches, gates, RTL, or behavioral code. Also, a designer needs to
learn only one language for stimulus and hierarchical design.
3. Most popular logic synthesis tools support Verilog HDL. This makes it the language of choice for
designers.
4. All fabrication vendors provide Verilog HDL libraries for post logic synthesis simulation. Thus, designing
a chip in verilog HDL allows the widest choice of vendors.
5. The Programming Language Interface (PLI) is a powerful feature that allows the user to write custom C
code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL
simulator to their needs with the PLI.

Assignment question:
1.Explain the CMOS fabrication process
2.Explain stick diagrams
3.Explain layout design rules
4.Explain the use of verilog VHDL in VLSI simulation.